• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.853-855
• /
• 1993

In this paper, a further improved system obtaining very low distorted waveforms of input ac currents of three phase rectifier circuit is proposed. The proposed system consists of an uncomplicated 24 pulse diode bridge rectifier that is transformerless, by adding only switching circuit which consists of two switchs to conventional system. Also to optimum the effectiveness or the harmonic reduction, the optimum turn ratio of an autotransformer and the optimum switching control angle are decided by computer simulation. And then, the voltage waveform obtained has a total harmonic distortion of 8.1%, and the predominant harmonics 23th and 25th. This paper describes operation principle, analysis of the waveforms of input voltage and current. The theoretial results are verified through simulation.

• Proceedings of the KIPE Conference
• /
• 2001.12a
• /
• pp.171-174
• /
• 2001

This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance .value is changed by the polarity of current or voltage. and this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit id constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduce and the power factor improve. A circuit design method is shown by experimentation and confirmed simulation. It explained that compared conventional pulse width modulated (PWM) inverter with half pulse-width modulated (HPWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.32-37
• /
• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• Proceedings of the KIPE Conference
• /
• 1999.07a
• /
• pp.362-365
• /
• 1999

In this paper, the method of reducing harmonics and correcting of power factor in single PWM converter associated with diode rectifier and boos converter is studied. The ac-dc converter in which the harmonic distortion in the input current is reduced using a third harmonic injected PWM is proposed. A lower switching power loss and easy configuration o control circuit are obtained by adopting discontinuous current mode. Simulation and experimental results of ac-dc converter with 5[KHz] switching frequency are presented and correction of power factor and reduction of total harmonic distortion was established.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.9
• /
• pp.1427-1435
• /
• 1990

This paper proposes the Selected Harmonic Elimination Pluse Width Modulation (SHE PW) scheme toreduce the ahrmonic components of source line current. To eliminate the low order harmonics which affects the source dominatly, we apply the Fourier series analysis to line current waveforms and then find out the switching patterns using the SHE PWM scheme. In addition to the analysis of harmonic effects, the three phase filter circuit is used to reduce high order harmonics. For the experimental realization, the converter circuit with power Transistor(PTR) is designed and the Pulse Time Control(PTC) is applied. The line current and the load voltage are measured under the condition of three phase application, highly inductive load.

• Proceedings of the KIEE Conference
• /
• 2006.07a
• /
• pp.220-221
• /
• 2006

This paper presents a single-phase parallel active power filter with an analog control circuit to eliminate for harmonic source currents generated by nonlinear loads. The proposed system removes the harmonic source currents by injecting a compensation current that is 180' out of phase with the load harmonic current. The detection of the load harmonics is realized by a simple new structure, referred to the Notch Filter with GIC (Generalized Impedance Converter), which has higher Q than existing harmonic detecters and a simpler structure. The compensation current is obtained using the proposed harmonic detection circuit, DC-Link voltage, and output current of the full-bridge inverter controlled current mode PWM controller. The operation of the proposed system is verified experimentally.

• Journal of Power Electronics
• /
• v.14 no.3
• /
• pp.572-579
• /
• 2014

As a non-linear time variant system, the four-quadrant line converter of an electric multiple unit (EMU) was expressed by linear time periodic functions near an operating point and modeled by a steady-state harmonic domain matrix. The components were then combined according to the circuit connection and relations of the feedback control loops to form a complete converter model. The proposed modeling method allows the study of the amplitude of harmonic impedances to explore harmonic coupling. Moreover, the proposed method helps provide a better design for the converter controllers, as well as solves the problem in coordination operation between the EMUs and the AC supply. On-site data from an actual $CRH_2$ high-speed train were used to validate the modeling principles presented in the paper.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.51 no.1
• /
• pp.23-33
• /
• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.1 no.3
• /
• pp.366-371
• /
• 2012

In this paper, we propose an electric circuit using one common-arm of H-Bridge inverters to reduce the number of switching components in the multi-level inverter combined with H-Bridge inverters and transformers. And furthermore, we suggested a new multi-level PWM inverter using PWM level to reduce THD (Total Harmonic Distortion). We use a phase-shift switching method that has the same rate of usage at each transformer. Also, we test the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of the control signal for the proposed multi-level PWM inverter.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1513-1522
• /
• 2018

This paper proposes a new islanding detection method for inverter-based distributed generators by continuously injecting a negligible amount of 2nd order harmonic current. The proposed method adopts a proportional resonant (PR) controller for the output current control of the inverter, and a PR filter to extract the 2nd order harmonic voltage at the point of common coupling (PCC). The islanding state can be detected by measuring the magnitude ratio of the 2nd order harmonic voltage to the fundamental voltage at the PCC by injecting a 2nd order harmonic current with a 0.8% magnitude. The proposed method provides accurate and fast detection under grid voltage unbalance and load unbalance. The operation of the proposed method has been verified through simulations and experiments with a 5kW hardware set-up, considering the islanding test circuit suggested in UL1741.