• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.2
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• pp.14-23
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• 2010

This paper analyzes braking performance of ABS with Sliding Mode Controller, which is designed in this research and compared with that of a commercial ABS-ECU only. HILS system for this paper has an existing hydraulic brake line with an ECU of commercial passenger vehicle and it is designed to be cooperated with Sliding Mode Controller and hydraulic line. This paper shows the simulation results to meet the target slip ratio on the various road conditions and displays the performance with Sliding Mode Controller has an improvement than a commercial ABS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.9
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• pp.1315-1322
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• 2015

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

• International Journal of Aeronautical and Space Sciences
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• v.4 no.1
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• pp.75-87
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• 2003

The primary objective of this study is to demonstrate ground-based experiment for the attitude control of spacecraft. A two-axis rotational simulator with a flexible ann is constructed with on-off air thrusters as actuators. The simulator is also equipped with payload pointing capability by simultaneous thruster and DC servo motor actuation. The azimuth angle is controlled by on-off thruster command while the payload elevation angle is controlled by a servo-motor. A thruster modulation technique PWM(Pulse Width Modulation) employing a time-optimal switching function plus integral error control is proposed. An optical camera is used for the purpose of pointing as well as on-board rate sensor calibration. Attitude control performance based upon the new closed-loop control law is demonstrated by ground experiment. The modified switching function turns out to be effective with improved pointing performance under external disturbance. The rate sensor calibration technique by Kalman Filter algorithm led to reduction of attitude error caused by the bias in the rate sensor output.

• Transactions of the Korean Society of Automotive Engineers
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• v.17 no.1
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• pp.162-168
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• 2009

The real-time multibody vehicle model based on the subsystem synthesis method has been developed. Suspension, anti roll bar, steering, and tire subsystem models have been developed for vehicle dynamics. The compliance effect from bush element has been considered using a quasi-static method to achieve the real time requirement. To validate the developed vehicle model, a quarter car and a full vehicle simulations have been carried out comparing simulation results with those from the ADAMS vehicle model. Real time capability has been also validated by measuring CPU time of the simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.299-306
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• 2010

This paper proposes a new doubly-fed induction generator (DFIG) system using a matrix converter controlled by direct duty ratio pulse-width modulation (DDPWM) scheme. DDPWM is a recently proposed carrier based modulation strategy for matrix converters which employs a triangular carrier and voltage references in a voltage source inverter. By using DDPWM, the matrix converter can directly and effectively generate rotor voltages following the voltage references within the closed control loop. The operation of the proposed DFIG system was verified through computer simulation and experimental works with a hardware simulator of a wind power turbine, which was built using a motor-generator set with vector drive. The simulation and experimental results confirm that a matrix converter with a DDPWM modulation scheme can be effectively applied for a DFIG wind power system.

• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.69-81
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• 2001

This paper describes a parallel programming environment to help programmer to write parallel programs. Parallel program must be write according to the character of the various hardware or program. So it is difficult for the programs to write the parallel programmer. In this paper, we propose and implement a parallel programming environment using graph type intermediate representation form, and graph user interface is provided for programmer to get parallel programs easily, This parallel environment supports special functions using graph type intermediate representation form. The special functions involve program editing. data dependence analysis, loop transformation. CFG, PDG, HTG. This parallel environment helps users make parallelism and optimization easy through showing the intermediate code with graph.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.6
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• pp.548-554
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• 2012

Verification and validation of operational software of the flight control computer, which is flight safety critical, is very important to prove correctness and faultness of the software. To verify the real-time softare requirement on operational software of flight control computer, real-time software internal parameter and variable monitoring technics on hardware-in-the-loop environment, similar to on-flight environment, is required. This paper describes flight safety critical software validation and verificiation environment using standard debugging interface, NEXUS 5001.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.18 no.5
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• pp.91-107
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• 2023

Lean startup is a concept that combines the words "lean," meaning an efficient way of running a business, and "startup," meaning a new business. It is often cited as a strategy for minimizing failure in early-stage businesses, especially in software-based startups. By scrutinizing the case of a startup L, this study suggests that lean startup methodology(LSM) can be useful for hardware and manufacturing companies and identifies ways for early startups to successfully implement LSM. To this end, the study explained the core of LSM including the concepts of hypothesis-driven approach, BML feedback loop, minimum viable product(MVP), and pivot. Five criteria to evaluate the successful implementation of LSM were derived from the core concepts and applied to evaluate the case of startup L . The early startup L pivoted its main business model from defecation alert system for patients with limited mobility to one for infants or toddlers, and finally to a smart bottle for infants. In developing the former two products, analyzed from LSM's perspective, company L neither established a specific customer value proposition for its startup idea and nor verified it through MVP experiment, thus failed to create a BML feedback loop. However, through two rounds of pivots, startup L discovered new target customers and customer needs, and was able to establish a successful business model by repeatedly experimenting with MVPs with minimal effort and time. In other words, Company L's case shows that it is essential to go through the customer-market validation stage at the beginning of the business, and that it should be done through an MVP method that does not waste the startup's time and resources. It also shows that it is necessary to abandon and pivot a product or service that customers do not want, even if it is technically superior and functionally complete. Lastly, the study proves that the lean startup methodology is not limited to the software industry, but can also be applied to technology-based hardware industry. The findings of this study can be used as guidelines and methodologies for early-stage companies to minimize failures and to accelerate the process of establishing a business model, scaling up, and going global.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.