• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of Korea Multimedia Society
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• v.18 no.6
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• pp.723-733
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• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.5
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• pp.1-8
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• 2013

This paper implements an integrated vehicle chassis system of ACC(Adaptive Cruise Control) and LKS(Lane Keeping System) based on OSEK OS to vehicle operating system and analyzes its performance through experiments. In recent years active safety and advanced driver assistance system has discussed to improve safety of vehicle. Among the rest, We integrate ACC that controls longitudinal velocity of vehicle and LKS that assists a vehicle in maintaing its driving lane, then implement integrated control system in vehicle. Implemented control system uses OSEK/VDX proposed standard, which is aiming at reusability and safety of software for vehicle and removal hardware dependence of application software. Redesigned control system based on OSEK OS, which is supported by OSEK/VDX, can manage real-time task, process interrupt and manage shared resource. We show by results performed EILS(ECU-In-the-Loop Simulation) that OSEK OS-based integrated controller of ACC and LKS is equivalent conventional integrated controller of ACC and LKS.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.12
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• pp.1905-1910
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• 2013

This paper demonstrates the result of Safety Integrity Level (SIL) allocation for IL-type Train Control System(IL-TCS), by applying the semi-quantitative approach. IL-type TCS is defined in this paper as the set of Hardware and Software ATS equipment, Track-side ATP equipment, On-board ATP equipment, Track-side ATO equipment, On-board ATO equipment. SIL allocation is performed for these constituent subsystems of TCS. Based on three principles of the semi-quantitative method, the SIL allocation process is performed for the subsystems composing TCS.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• ETRI Journal
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• v.39 no.4
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• pp.535-545
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• 2017

This paper presents a novel K-band (18 GHz) 16-quadrature amplitude modulation (16-QAM) orthogonal frequency-division multiplexing (OFDM)-based $2{\times}2$ line-of-sight multi-input multi-output communication system. The system can deliver 356 Mbps on a 56 MHz channel. Alignment mismatches, such as amplitude and/or phase mismatches, between the transmitter and receiver antennas were examined through hardware experiments. Hardware experimental results revealed that amplitude mismatch is related to antenna size, antenna beam width, and link distance. The proposed system employs an alignment mismatch compensation method. The open-loop architecture of the proposed compensation method is simple and enables facile construction of communication systems. In a digital modem, 16-QAM OFDM with a 512-point fast Fourier transform and (255, 239) Reed-Solomon forward error correction codecs is used. Experimental results show that a bit error rate of $10^{-5}$ is achieved at a signal-to-noise ratio of approximately 18.0 dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.133-137
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• 2018

Arduino is a small microcomputer that is used in a variety of industry fields and especially is widely used as an open source hardware IoT device. The multi-tasking method of Arduino is divided into super loop timing and RTOS thread method. The super loop timing method is simple and easy to understand. However, when one task is long, it affects the execution of the next task. In addition, RTOS threading has the advantage of being able to run without being influenced by other work time. However, Arduino, a small microcomputer, has a disadvantage in that, when the number of threads increases, the context switching time of the thread causes additional time not included in the super loop timing method have. In this paper, we use Arduino Uno R3 and FreeRTOS to analyze these different features, and the task for the experiment is to send 8000 digital signals to the built-in LED port. If two tasks of the same size are executed, the super loop method executes 3 ms faster than FreeRTOS multitasking. If multiple tasks are executed simultaneously, superloop type task is sequential execution and difference in execution time between first task and last task is large. FreeRTOS method can be executed concurrently, but execution time delay of about 30 ms occurs in context switching time.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.294-297
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• 2021

A grid voltage estimation method for modular plug-in active power decoupling (APD) circuits is proposed in this study as direct replacements of electrolytic capacitors. Since modular plug-in APD circuits cannot have additional grid voltage sensors and should be operated independently without information exchange with the front-end converter, it is impossible to obtain the phase information of the grid directly. Therefore, the proposed method uses the second-order harmonic component of the DC-link voltage to estimate the grid voltage necessary to control the APD circuit. By employing the proposed method, the concept of modular plug-in APD circuits can be realized and implemented without direct detection of the grid voltage. The experimental results based on hardware-in-the-loop simulation (HILS) validate the effectiveness of the proposed control method.