• 제어로봇시스템학회:학술대회논문집
• /
• 2000.10a
• /
• pp.216-216
• /
• 2000

In this paper, we introduce a new roadway-departure prevention algorithm and the developed Hardware-in-the-Loop-Simulator (HiLS) for applying the new algorithm. A sliding-mode controller is used for lateral position control. And, the HiLS consists of real car elements, a micro-control board, and a self-aligning torque generator Finally from the display module, the perspective view and bird view of the animated vehicle can be seen simultaneously.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.1346-1349
• /
• 2002

This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

• Journal of Advanced Marine Engineering and Technology
• /
• v.32 no.3
• /
• pp.437-445
• /
• 2008

This paper deals with the experimental assessment of the vibration suppression of the smart structures. First. we have presented a new high-speed active control system using the DSP320C6713 microprocessor. A peripheral system developed is composed of a data acquisition system, N/D and D/A converters, piezoelectric (PZT) actuator/sensors, and drivers for fast data processing. Next, we have tested the processing time of the peripheral devices, and provided the corresponding test results. Since fast data processing is very important in the active vibration control of the structures, we have focused on achieving the fast loop times of the control system. Finally, numerous experiments were carried out on the aluminum plate to validate the superior performance of the vibration control system at different control loop times.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.249-250
• /
• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.8
• /
• pp.22-38
• /
• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.345-348
• /
• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.6
• /
• pp.9-14
• /
• 2002

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.12C
• /
• pp.1029-1034
• /
• 2010

For All Digital QPSK receivers, a phase recovery scheme is required to fix the arbitrarily rotated I/Q quadrature signals due to the transmission path and clock mismatch between the transmitter and the receiver. The conventional Costas phase recovery loop scheme requires a separate AGC(Automatic Gain Control) to obtain the performance independent of input signal power. This paper proposes a simple scheme which separates the phase and amplitude of the input signal via CORDIC algorithm and performs the phase recovery and amplitude compensation simultaneously. The proposed scheme can considerably reduce the logic resources in hardware implementation, has been verified by C++ and Model Sim simulations.

• Proceedings of the Korea Society for Simulation Conference
• /
• 1999.04a
• /
• pp.88-92
• /
• 1999

As a part of work to simulate electromagnetic environments for Hardware-In-the-Loop(HIL) simulation, the dynamic trajectory is modeled by the Way-points method and the Event-driven method for the aerial and the naval targets. The simulated results show that the Way-points method and the Event-driven method are appropriate to simulate a low speed and a high speed target respectively.

• Journal of Korean Institute of Industrial Engineers
• /
• v.25 no.2
• /
• pp.282-289
• /
• 1999

To minimize a real world test of underwater guided vehicle, it is necessary to perform a test on ground by using closed loop test techniques. This paper describes implementation of HILS(Hardware In the Loop Simulation) system for ground test and test methodologies for performance evaluation of a guided weapon. HILS system uses a real time distributed computer and a real time processing technique. Ground test results of underwater vehicle are presented for moving and stationary targets by using HILS system.