• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.1
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• pp.17-24
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• 2012

Recently automotive software has been more complex and needs to be reduced its development time. Software testing of its functionalities and performance should be conducted in an early development phase to reduce time to market and the development cost. Software functional testing can be performed through simulating the hardware, but it is not guaranteed that evaluation of real-time performance using simulation has enough accuracy. Real-time performance can be precisely evaluated with hardware-in-the-loop simulation, but it costs time and effort to set up hardware for testing. In this paper, we suggest a testing system that can evaluate functional requirements and real time properties with a general-purpose development board in the early development phase. In addition, we improve reusability of the testing system through modularized and layered architecture. With the proposed testing system we can contribute to building reliable testing system at low cost without difficulty.

• 전기의세계
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• v.25 no.5
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• pp.59-62
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• 1976

Applications of the digital computers in the control systems are not new. But when one tries to integrate the control system with a digital computer to form a feedback loop, he has to solve a great deal of problems in both hardware and software aspects. Such problems are investigated in this paper. For the hardware aspect, one has to design interfaces for both ADC and DAC. Since these are absolutely necessary pieces of hardware, one can notavoid from using them. The interface which employ the programmed data transfer method was designed for this research. For the software aspect, one has to build models for the digital compensator and the controlled system. In order to do that it is necessary to utilize the real time clock and to write his own interrupt service routine. As a sample case, a deadbeat compensator was desinged and tested.

• Transactions of The Korea Fluid Power Systems Society
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• v.5 no.4
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• pp.1-9
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• 2008

In this paper, an energy regeneration algorithm is proposed to make the maximum use of the regenerative braking energy for a parallel hybrid electric vehicle(HEV) equipped with a continuous variable transmission(CVT). The regenerative algorithm is developed by considering the battery state of charge(SOC), vehicle velocity and motor capacity. The hydraulic module consists of a reducing valve and a power unit to supply the front wheel brake pressure according to the control algorithm. In order to evaluate the performance of the regenerative braking algorithm and the hydraulic module, a hardware-in-the-loop simulation (HILS) is performed. In the HILS system, the brake system consists of four wheel brakes and the hydraulic module. Dynamic characteristics of the HEV are simulated using an HEV simulator. In the HEV simulator, each element of the HEV powertrain such as internal combustion engine, motor, battery and CVT is modelled using MATLAB/$Simulink^{(R)}$. In the HILS, a driver operates the brake pedal with his or her foot while the vehicle speed is displayed on the monitor in real time. It is found from the HILS that the regenerative braking algorithm and the hydraulic module suggested in this paper provide a satisfactory braking performance in tracking the driving schedule and maintaining the battery state of charge.

• Annual Conference of KIPS
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• 2013.11a
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• pp.1506-1509
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• 2013

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 in-loop filter의 하드웨어 구조 설계에 대해 기술한다. in-loop filter는 deblocking filter와 SAO로 구성되며, 블록 단위 영상 압축 및 양자화 등에서 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC는 $64{\times}64$ 블록 크기까지 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 in-loop filter의 deblocking filter 모듈과 SAO 모듈은 최소 연산 단위인 $8{\times}8$ 블록 연산기로 구성하여 하드웨어 면적을 최소화하였다. 또한 SAO에서는 $8{\times}8$ 블록의 연산 결과를 내부레지스터에 저장하는 구조로 $64{\times}64$ 블록 크기를 지원하도록 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 180nm 셀 라이브러리로 합성한 결과 동작 주파수는 270MHz이고, 전체 게이트 수는 48.9k이다.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.588-593
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• 1987

In this study, direct-drive position controllers are designed and implemented for the flying vehicles actuating system with both positive and negative load factors, where the load factors are assumed proportional to the deflection angle of control surface. Its analog and digital controllers are verified through software simulation and hardware-in-the-loop simulation.

• Journal of the korean Society of Automotive Engineers
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• v.15 no.5
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• pp.8-14
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• 1993

본 고에서는 실시간 Hardware-in-the-loop 시뮬레이션의 기술 현황 및 적용 분야를 알아보고, 차량 동력학 분야에 있어서, 실시간 시뮬레이션의 구현을 위해 확보되어야 할 하드웨어 및 소프트웨어 환경에 대한 고찰과 이를 이용한 시스템 설계를 소개하고자 한다.

• Journal of Astronomy and Space Sciences
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• v.27 no.4
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• pp.377-382
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• 2010

In lunar explorer development program, computer simulator is necessary to provide virtual environments that vehicle confronts in lunar transfer, orbit, and landing missions, and to analyze dynamic behavior of the spacecraft under these environments. Objective of simulation differs depending on its application in spacecraft development cycle. Scope of use cases considered in this paper includes simulation of software based, processor and/or hardware in the loop, and support of ground-based flight test of developed vehicle. These use cases represent early phase in development cycle but reusability of modeling results in the next design phase is considered in defining requirements. A simulator architecture in which simulator platform is located in the middle and modules for modeling, analyzing, and three dimensional visualizing are connected to that platform is suggested. Baseline concepts and requirements for simulator development are described. Result of trade study for selecting simulation platform and approaches of defining other simulator components are summarized. Finally, characters of lunar elevation map data which is necessary for lunar terrain generation is described.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1496-1504
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• 2019

This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.223-224
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• 2008

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.