• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.10
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• pp.458-464
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• 1986

This paper introduces a method for design verification and performance evaluation of flight control system. The method is a real time hardware in the loop simulation using the hybrid computer and motion table facility. As a typical illustration, a roll control system of flight vehicle is applied. The simulation validity is demonstrated by comparing hardware test results with analog simulation results.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.969-973
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• 2005

This paper presents a survey of software reliability modeling and it's application to pre-built software system combined with hardware such as numerical controller based on personal computer systems. Many a systems in these days are much more becoming software intensive and many software intensive systems are safety critical. For this reason, the technique well developed to measure of software reliability is very important for whom to assess such a system. This paper provides a brief idea of method to evaluate such a system's reliability based on hardware performance.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.466-470
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• 1993

A HILS(Hardware-In-the-Loop Simulation) technique for an IR guided weapon is proposed. The IR HILS facility functions as a testing unit for a missile guidance and control system to evaluate target acquisition, tracking, and countermeasure performance. The configuration of IR HILS facility, modeling technique of an IR environment including target, background and countermeasure, and test and evaluation procedure are included.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.749-758
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• 1995

There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.425-433
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• 1999

This paper describes a simulation model and a scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which can flexibly adjust the active and reactive power flow through the ac transmission line. The design of control system was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. And both models are very effective to analyze the dynamic performance of the Unified Power Flow Controller.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2659-2661
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• 2002

The development of guided missile requires complex guidance schemes and hardware units because of high maneuver, delicate and variable missions. In this point of view, simulation systems and facilities which test missile hardwares and softwares are needed. This paper introduces the hardware-in-the loop simulation system and facilities which include the real-time computation systems and 3 Axis FMS(Flight Motion Simulator).

• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.132-148
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• 2002

In this paper, development procedures of an Underwater Vehicle HILS/MILS System in SE(Synthetic Environment) are described. As this System is developed, we can obtain the more powerful tool which can be used to test and verify operational logics and algorithms of an Underwater Vehicle as well as its hardware in various tactical situations.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.