• Title/Summary/Keyword: Hardware limitation

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Performance Analysis of Full Duplex on-regenerative Relay

  • Ban, Tae-Won;Jung, Bang-Chul
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.647-651
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    • 2011
  • In this letter, non-regenerative Amplify-and-Forward (AF) relay systems based on half and full duplex schemes are investigated and their performance is analyzed and compared in terms of outage probability. Although the AF relay systems have been widely investigated in many previous literatures, most of them adopted a half duplex scheme due to hardware limitation and mathematical tractability. To the best of our knowledge, this letter is the first study to investigate the performance of the full duplex AF relay system considering practical hardware limitations. In full duplex AF relay systems, it is important to secure the isolation between transmit and receive antennas. Our numerical and simulation results show that there exists a threshold point of the isolation gain that the full duplex relay system outperforms the half duplex relay system.

Efficient Native Processing Modules for Interactive DTV Middleware Based on the Small Footprint Set-Top Box

  • Shin, Sang-Myeong;Im, Dong-Gi;Jung, Min-Soo
    • Journal of Korea Multimedia Society
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    • v.9 no.12
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    • pp.1617-1627
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    • 2006
  • The concept of middleware for digital TV receivers is not new one. Using middleware for digital TV development has a number of advantages. It makes it easier for manufacturers to hide differences in the underlying hardware. It also offers a standard platform for application developers. Digital TV middleware enables set-top boxes(STBs) to run video, audio, and applications. The main concern of digital TV middleware is now to reduce its memory usage because most STBs in the market are small footprint. In this paper, we propose several ideas about how to reduce the required memory size on the runtime area of DTV middleware using a new native process technology. Our proposed system has two components; the Efficient Native Process Module, and Enhanced Native Interface APIs for concurrent native modules. With our approach, the required memory reduced from 50% up to 75% compared with the traditional approach. It can be suitable for low end STBs of very low hardware limitation.

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Effects of the Sampling Time in Motion Controller Implementation for Mobile Robots (모바일 로봇 모션 제어에 있어 샘플링 시간의 효과)

  • Jang, Tae-Ho;Kim, Youngshik
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.37 no.4
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    • pp.154-161
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    • 2014
  • In this research we investigate motion controller performance for mobile robots according to changes in the control loop sampling time. As a result, we suggest a proper range of the sample time, which can minimize final posture errors while improving tracking capability of the controller. For controller implementation into real mobile robots, we use a smooth and continuous motion controller, which can respect robot's path curvature limitation. We examine motion control performance in experimental tests while changing the control loop sampling time. Toward this goal, we compare and analyze experimental results using two different mobile robot platforms; one with real-time control and powerful hardware capability and the other with non-real-time control and limited hardware capability.

Hybrid Sinusoidal-Pulse Charging Method for the Li-Ion Batteries in Electric Vehicle Applications Based on AC Impedance Analysis

  • Hu, Sideng;Liang, Zipeng;He, Xiangning
    • Journal of Power Electronics
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    • v.16 no.1
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    • pp.268-276
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    • 2016
  • A hybrid sinusoidal-pulse current (HSPC) charging method for the Li-ion batteries in electric vehicle applications is proposed in this paper. The HSPC charging method is based on the Li-ion battery ac-impedance spectrum analysis, while taking into account the high power requirement and system integration. The proposed HSPC method overcomes the power limitation in the sinusoidal ripple current (SRC) charging method. The charger shares the power devices in the motor inverter for hardware cost saving. Phase shifting in multiple pulse currents is employed to generate a high frequency multilevel charging current. Simulation and experimental results show that the proposed HSPC method improves the charger efficiency related to the hardware and the battery energy transfer efficiency.

Trends of the CCIX Interconnect and Memory Expansion Technology (CCIX 연결망과 메모리 확장기술 동향)

  • Kim, S.Y.;Ahn, H.Y.;Jun, S.I.;Park, Y.M.;Han, W.J.
    • Electronics and Telecommunications Trends
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    • v.37 no.1
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    • pp.42-52
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    • 2022
  • With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

Study of Hardware AES Module Backdoor Detection through Formal Method (정형 기법을 이용한 하드웨어 AES 모듈 백도어 탐색 연구)

  • Park, Jae-Hyeon;Kim, Seung-joo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.29 no.4
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    • pp.739-751
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    • 2019
  • Security in embedded devices has become a significant issue. Threats on the sup-ply chain, like using counterfeit components or inserting backdoors intentionally are one of the most significant issues in embedded devices security. To mitigate these threats, high-level security evaluation and certification more than EAL (Evaluation Assurance Level) 5 on CC (Common Criteria) are necessary on hardware components, especially on the cryptographic module such as AES. High-level security evaluation and certification require detecting covert channel such as backdoors on the cryptographic module. However, previous studies have a limitation that they cannot detect some kinds of backdoors which leak the in-formation recovering a secret key on the cryptographic module. In this paper, we present an expanded definition of backdoor on hardware AES module and show how to detect the backdoor which is never detected in Verilog HDL using model checker NuSMV.

Eddy current compensation using a gradient system modeling in MR Spiral scan imaging (MR Spiral scan 영상에서 Gradient system의 모델링을 이용한 Eddy current compensation)

  • Cho, S.H.;Kim, P.K.;Kang, S.W.;Ahn, C.B.
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.339-340
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    • 2007
  • Gradient system에 spiral waveform 입력을 가하면 Hardware limitation에 의하여 만들어지는 gradient fields에 Transient time delay가 발생한다. 이를 보상하기 위하여, Gradient system을 R-L-C 회로로 모델링하여 재구성에 필요한 k-space trajectory를 보정하여 개선된 image를 획득하였다.

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A Hardware Architecture of Regular Expression Pattern Matching for Deep Packet Inspection (심층 패킷검사를 위한 정규표현식 패턴매칭 하드웨어 구조)

  • Yun, Sang-Kyun;Lee, Kyu-Hee
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.5
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    • pp.13-22
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    • 2011
  • Network Intrusion Detection Systems use regular expression to represent malicious packets and hardware-based pattern matching is required for fast deep packet inspection. Although hardware architectures for implementing constraint repetition operators such as {10} were recently proposed, they have some limitation. In this paper, we propose hardware architecture supporting constraint repetitions of general regular expression sub-patterns with lower logic complexity. The subpatterns supported by the proposed contraint repetition architecture include general regular expression patterns as well as a single character and fixed length patterns. With the proposed building block, we can implement more efficiently regular expression pattern matching hardwares.

Rapid Prototyping of Head-of-Bed Angle Measurement System using Open-Source Hardware (오픈소스하드웨어를 이용한 침상머리각도 측정 시스템의 래피드 프로토타이핑)

  • Jo, Bong-Un;Park, Yeong-Sang;Seo, Sugkil;Kim, Jin-Geol;Lee, Young-Sam
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.11
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    • pp.1038-1043
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    • 2015
  • When the study on the relationship between the Head-of-Bed (HOB) angle and ventilator-associated pneumonia is performed, the fact that the HOB angle can only be measured intermittently imposes a significant limitation on the study. Therefore, there has been demand for the development of a device that can measure the HOB angle continuously. In this paper, we propose the rapid prototyping of an HOB measurement system using open-source hardware and software. The proposed system helps to maintain the HOB angle at a particular angle by displaying the angle and helps the medical study of pneumonia patients by enabling continuous data acquisition. Firstly, we eliminate the process of making an MCU board by utilizing an open-source hardware mbed LPC1768. Secondly, we reduce the software development time by using libraries and hence enabling the easy use of peripherals. Thirdly, for rapid prototyping, we build the enclosure of the proposed system using a 3D printer. The proposed system can be attached and detached to and from a bed. Therefore, we can attach it to the bed of a patient for whom measurement of the HOB angle is necessary. Finally, we check the measurement performance and the validity of the proposed system through an experiment utilizing an incremental encoder.

A Non-volatile Memory Lifetime Extension Scheme Based on the AUTOSAR Platform using Complex Device Driver (AUTOSAR 플랫폼 기반 CDD를 활용한 비휘발성 메모리 수명 연장 기법)

  • Shin, Ju-Seok;Son, Jeong-Ho;Lee, Eun-Ryung;Oh, Se-Jin;Ahn, Kwang-Seon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.5
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    • pp.235-242
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    • 2013
  • Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.