• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.84.5-84
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• 2002

In order to be a stand-alone structure, a biped robot should be designed of the effective mechanic structure and the smaller hardware system. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU and FPGA as the motor controller...

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.56-68
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• 2003

Difficult problems In implementing digital neural network hardware are the extension of synapses and the programmability for relocating neurons. In this paper, the structure of a new hardware is proposed for solving these problems. Our structure based on traditional SIMD can be dynamically and easily reconfigured connections of network without synthesizing and mapping original design for each use. Using additional modular processing unit the numbers of neurons find synapses increase. To show the extensibility of our structure, various models of neural networks : multi-layer perceptrons and Kohonen network are formed and tested. The performance comparison with software simulation shows its superiority in the aspects of performance and flexibility.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.118-125
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• 2008

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.206-215
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• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.711-714
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• 2000

In this paper, we propose a high-speed multiplier-free realization using ROM’s to store the results of coefficient scalings in Combination With higher signal rate and pipelined operations. We show that hardware multipliers are not needed. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or through-put). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that With Proper Choices of the Parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.