• Proceedings of the Korea Information Assurance Society Conference
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• 2004.05a
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• pp.59-64
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• 2004

In this paper a design and an implementation of a crypto chip which implements SEED and Triple-DES algorithms are described. We designed it by VHDL(VHSIC Hardware Description Language) which is a designed system-description language. To apply the chip to various application, four operating Modes such as ECB, CBC, CFB, and CFB are supported. The chip was designed by the Virtex-E XCV2000E BG560 of Xilinx and we confirmed result of it at the FPGA implementation by functional and timing simulation using the Xilinx Foundation Series 3.li.

• Journal of the Optical Society of Korea
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• v.20 no.3
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• pp.335-342
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• 2016

We demonstrate an optical asynchronous transfer mode/wavelength division multiplexing (OATM/WDM) optical access network, using a router based on an optical header decoder to conduct next-generation communications. The router consists of a decoder or hardware analysis processing of the header bit and switches. The router in the OATM/WDM optical access network is a key technology by which to satisfy subscribers’ requests, including reliability, cost efficiency, high speed, large-capacity transmission, and elevated information security. In this study, we carry out experiments in which a header decoder delivers to 16 and 32 subscribers with a single wavelength in the router. These experiments confirm the decoder’s successful operation via hardware using 4 and 5 header bits. We propose that this system may significantly contribute toward the realization of an optical access network that provides high-quality service to subscribers of next-generation communications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.803-806
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• 2005

In this paper, we analyses of Architecture for High-speed authentication protocol in wireless communication. The rapid process in wireless communication systems, personal communications, and smartcard technologies has brought new opportunities and challenges to be met by engineers and researchers working on the security aspects of the new communication. In real world, we have restricted hardware environments with limited computational power and small memory, we meet more challenges. Then we analyes the need of consideration to implement the system.

• Design & Manufacturing
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• v.16 no.3
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• pp.34-38
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• 2022

Regular expression pattern matching is widely used in applications such as computer virus vaccine, NIDS and DNA sequencing analysis. Hardware-based pattern matching is used when high-performance processing is required due to time constraints. ReCPU, SMPU, and REMP, which are processor-based regular expression matching processors, have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based regular expression matching processors inefficiently handle repetitive operations of regular expressions. In this paper, we propose a new instruction set to improve the inefficient repetitive operations of ReCPU and SMPU. We propose REMPi, a regular expression matching processor that enables efficient iterative operations based on the REMP instruction set. REMPi improves the inefficient method of processing a particularly short sub-pattern as a repeat operation OR, and enables processing with a single instruction. In addition, by using a down counter and a counter stack, nested iterative operations are also efficiently processed. REMPi was described with Verilog and synthesized on Intel Stratix IV FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4794-4800
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• 2012

Many researches have been performed to resist buffer overflow attacks. However, the attack still poses one of the most important issue in system security field. It is because programmers are using library functions containing security hole and once buffer overflow vulnerability has been found, the security patches are distributed after the attacks are widely spreaded. In this paper, we propose a new cache level return address stack architecture for resisting buffer overflow attack. We implemented our hardware onto SimpleScalar simulator and verified its functionality. Our circuit can overcome the various disadvantages of previous works with small overhead.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.2
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• pp.786-799
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• 2018

Recently, NFV has attracted attention as a next-generation network virtualization technology for hardware -independent and efficient utilization of resources. NFV is a technology that not only virtualize computing, server, storage, network resources based on cloud computing but also connect Multi-Tenant of VNFs, a software network function. Therefore, it is possible to reduce the cost for constructing a physical network and to construct a logical network quickly by using NFV. However, in NFV, when a new VNF is added to a running Tenant, authentication between VNFs is not performed. Because of this problem, it is impossible to identify the presence of Fake-VNF in the tenant. Such a problem can cause an access from malicious attacker to one of VNFs in tenant as well as other VNFs in the tenant, disabling the NFV environment. In this paper, we propose Auto-configurable Security Mechanism in NFV including authentication between tenant-internal VNFs, and enforcement mechanism of security policy for traffic control between VNFs. This proposal not only authenticate identification of VNF when the VNF is registered, but also apply the security policy automatically to prevent malicious behavior in the tenant. Therefore, we can establish an independent communication channel for VNFs and guarantee a secure NFV environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7C
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• pp.640-648
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• 2009

Summation generator with high period and high linear complexity can be easily implemented by a simple hardware or software and it is proper to apply in mobile security system for ubiquitous environments. However the generator has been some weaknesses from Dawson's divided-and-conquer attack, Golic's correlation attack and Meier's fast correlation attack. In this paper, we propose an improved version($2^{128}$security level) of $E_0$algorithm, CVC-NSG(Circular-Clock-Controlled - Nonlinear Summation Generator), which partially replaces LFSRs with nonlinear FSRs and controls the irregular clock to reinforce it's own weaknesses. Finally, we analyze our proposed design in terms of security and performance.

• Convergence Security Journal
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• v.15 no.6_2
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• pp.89-97
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• 2015

The Smart phone is the mobile phone added to mounted equipment miniaturized operating system of PC and wireless phone possible hardware, software modules. This study is examine about Smart phone supply spreading process and characteristic by age. And this study is wish to investigate about age-based features of the media usage attitude via a Smart phone as a reference questionnaire of KISA and KISDI. Smart phone is easy-to-use and excellent portability and mobility like Pocket PC. It is easy to information and data search anytime and anywhere unaffected by time and place. It is to possible a variety of information exchange with several acquaintances and easy to photos and video photography. Wish to improve the life satisfaction with widely using for smart phones at all ages.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.9-16
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• 2004

This paper proposes a performance analysis model of security servers comprising IPSec accelerators. The proposed model is based on a M/M1 queueing system with traffic load of Poisson distribution. The decoding delay has been defined to cover parameters characterizing hardware of security sorrels. Decoding delay values of a commercial IPSec accelerator are extracted yielding less than 15% differences from measured data. The extracted data are used to simulate the server system with the proposed model. The simulated performance of the cryptographic processor BCM5820 is around 75% of the published claimed level. The performance degradation of 3.125% and 14.28% are observed for 64byte packets and 1024byte packets, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.1
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• pp.99-107
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• 2005

ARIA is a 128-bit block cipher having 128-bit, 192-bit, or 256-bit key length. The cipher is a substitution and permutation encryption network (SPN) and uses an involutional binary matrix. This structure was efficiently developed into light weight environments or hardware implementations. This paper shows that a careless implementation of an ARIA on smartcards is vulnerable to a differential power analysis attack This attack is realistic because we can measure power consumption signals at two kinds of S-boxes and two types of substitution layers. By using the two round key, we extracted the master key (MK).