• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2974-2976
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• 1999

본 논문에서는 단일패턴과 다중패턴 학습이 가능한 FNNs(Feedforward Neural Networks)을 하드웨어로 구현하는데 필요한 학습방안을 제안한다. 제안된 학습방안은 기존의 하드웨어 구현에 이용되는 방식과는 전혀 다른 방식이며, 오히려 기존의 소프트웨어 학습방식과 유사하다. 기존의 하드웨어 구현에서 사용되는 방법은 오프라인 학습이나 단일패턴 온 칩(on-chip) 학습방식인데 반해, 제안된 학습방식은 단일/다중패턴은 칩 학습방식으로 다층 FNNs 회로와 학습회로 사이에 스위칭 회로를 넣어 구현되었으며, FNNs의 학습회로는 선형 시냅스 회로와 선형 곱셈기 회로를 사용하여MEBP(Modified Error Back-Propagation) 학습규칙을 구현하였다. 제안된 방식은 기존의 CMOS 공정으로 구현되었고 HSPICE 회로 시뮬레이터로 그 동작을 검증하였다 구현된 FNNs은 어떤 학습패턴 쌍에 의해 유일하게 결정되는 출력 전압을 생성한다. 제안된 학습방안은 향후 학습 가능한 대용량 신경망의 구현에 매우 적합하리라 예상된다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.71-77
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• 2021

Recently, there is a demand for efficient program development of an IoT application support frameworks considering heterogeneous hardware characteristics. In addition, the scope of hardware support is expanding with the development of neuromorphic architecture that mimics the human brain to learn on their own and enables autonomous computing. However, most existing IoT IDE(Integrated Development Environment), it is difficult to support AI(Artificial Intelligence) or to support services combined with various hardware such as neuromorphic architectures. In this paper, we design an AI component abstract model that supports the second-generation ANN(Artificial Neural Network) and the third-generation SNN(Spiking Neural Network), and implemented an autonomous IoT IDE based on the proposed model. IoT developers can automatically create AI components through the proposed technique without knowledge of AI and SNN. The proposed technique is flexible in code conversion according to runtime, so development productivity is high. Through experimentation of the proposed method, it was confirmed that the conversion delay time due to the VCL(Virtual Component Layer) may occur, but the difference is not significant.

• 한국HCI학회:학술대회논문집
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• 2007.02c
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• pp.322-325
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• 2007

Graphics processing unit (GPU) is used for a faster artificial neural network. It is used to implement the matrix multiplication of a neural network to enhance the time performance of a text detection system. Preliminary results produced a 20-fold performance enhancement using an ATI RADEON 9700 PRO board. The parallelism of a GPU is fully utilized by accumulating a lot of input feature vectors and weight vectors, then converting the many inner-product operations into one matrix operation. Further research areas include benchmarking the performance with various hardware and GPU-aware learning algorithms. (c) 2004 Pattern Recognition Society. Published by Elsevier Ltd. All rights reserved.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.248-250
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• 1993

In this paper, we assume that the dynamics of DC motor and nonlinear load are unknown. We train the inverse dynamic model of DC motor and nonlinear load using the neural network and construct speed control system based on the traind dynamic model and current control mode. Speed prediction scheme using neural network is also proposed the alleviate the time delay effect caused by the computation time of neural network. Simulation results show good performances of the control system. Finally, hardware configuration of the control system is outlined.

• The Journal of the Korea Contents Association
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• v.7 no.6
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• pp.44-51
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• 2007

For real-time recognizing of model objects in remote position a new Neural Networks algorithm is proposed. The proposed neural networks technique is the real time computation methods through the inter-node diffusion. In the networks, a node corresponds to a state in the quantized input space. Each node is composed of a processing unit and fixed weights from its neighbor nodes as well as its input terminal. The most reliable algorithm derived for real time recognition of objects, is a dynamic programming based algorithm based on sequence matching techniques that would process the data as it arrives and could therefore provide continuously updated neighbor information estimates. Through several simulation experiments, real time reconstruction of the nonlinear image information is processed. 1-D LIPN hardware has been composed and various experiments with static and dynamic signals have been implemented.

• Proceedings of the Korea Association of Information Systems Conference
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• 2000.11a
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• pp.1.2-24
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• 2000

The field of neural networks has been a recent surge in activity as a result of progress in developments of efficient training algorithms. For this reason, and coupled with the widespread availability of powerful personal computer hardware for running simulations of networks, there is increasing focus on the potential benefits this field can offer. The neural network may be viewed as an advanced pattern recognition technique and can be applied in many areas such as financial time series forecasting, medical diagnostic expert system and etc.. The intention of this study is to build and implement one simple artificial neural networks hereinafter called ANN. For this purpose, some literature survey was undertaken to understand the structures and algorithms of ANN theoretically. Based on the review of theories about ANN, the system adopted 3-layer back propagation algorithms as its learning algorithm to simulate one case of medical diagnostic model. The adopted ANN algorithm was performed in PC by using turbo PASCAL and many input parameters such as the numbers of layers, the numbers of nodes, the number of cycles for learning, learning rate and momentum term. The system output more or less successful results which nearly agree with goals we assumed. However, the system has some limitations such as the simplicity of the programming structure and the range of parameters it can dealing with. But, this study is useful for understanding general algorithms and applications of ANN system and can be expanded for further refinement for more complex ANN algorithms.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.270-279
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• 2000

This paper describes the on-chip learning algorithm of neural networks using the stochastic pulse arithmetic. Stochastic pulse arithmetic is the computation using the numbers represented by the probability of 1' and 0's occurrences in a random pulse stream. This stochastic arithmetic has the merits when applied to neural network ; reduction of the area of the implemented hardware and getting a global solution escaping from local minima by virtue of the stochastic characteristics. And in this study, the on-chip learning algorithm is derived from the backpropagation algorithm for effective hardware implementation. We simulate the nonlinear separation problem of the some character patterns to verify the proposed learning algorithm. We also had good results after applying this algorithm to recognize printed and handwritten numbers.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.4
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• pp.53-62
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• 2021

Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.

• Journal of Computing Science and Engineering
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• v.12 no.1
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• pp.24-35
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• 2018

Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

• Journal of Multimedia Information System
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• v.3 no.3
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• pp.91-96
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• 2016

Network security is an interesting area in Information Technology. It has an important role for the manager monitor and control operating of the network. There are many techniques to help us prevent anomaly or malicious activities such as firewall configuration etc. Intrusion Detection System (IDS) is one of effective method help us reduce the cost to build. The more attacks occur, the more necessary intrusion detection needs. IDS is a software or hardware systems, even though is a combination of them. Its major role is detecting malicious activity. In recently, there are many researchers proposed techniques or algorithms to build a tool in this field. In this paper, we improve the performance of IDS. We explore and analyze the impact of activation functions applying to recurrent neural network model. We use to KDD cup dataset for our experiment. By our experimental results, we verify that our new tool of IDS is really significant in this field.