• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.216-216
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• 2000

In this paper, we introduce a new roadway-departure prevention algorithm and the developed Hardware-in-the-Loop-Simulator (HiLS) for applying the new algorithm. A sliding-mode controller is used for lateral position control. And, the HiLS consists of real car elements, a micro-control board, and a self-aligning torque generator Finally from the display module, the perspective view and bird view of the animated vehicle can be seen simultaneously.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1346-1349
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• 2002

This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

• Journal of Advanced Marine Engineering and Technology
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• 제32권3호
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• pp.437-445
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• 2008

This paper deals with the experimental assessment of the vibration suppression of the smart structures. First. we have presented a new high-speed active control system using the DSP320C6713 microprocessor. A peripheral system developed is composed of a data acquisition system, N/D and D/A converters, piezoelectric (PZT) actuator/sensors, and drivers for fast data processing. Next, we have tested the processing time of the peripheral devices, and provided the corresponding test results. Since fast data processing is very important in the active vibration control of the structures, we have focused on achieving the fast loop times of the control system. Finally, numerous experiments were carried out on the aluminum plate to validate the superior performance of the vibration control system at different control loop times.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 전자공학회논문지C
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• 제34C권8호
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.345-348
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• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• 한국정밀공학회지
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• 제19권6호
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• pp.9-14
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• 2002

• 한국통신학회논문지
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• 제35권12C호
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• pp.1029-1034
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• 2010

QPSK 디지털 수신기는 전송 경로 또는 송수신기 간의 클럭 차이에 의해 발생하는 위상 편차를 보정하기 위해 위상 복원 방안이 필요하다. 널리 사용되고 있는 디지털 Costas 위상 복원 루프는 입력신호의 주파수/위상 복원 성능이 입력 신호의 전력에 따라 달라지므로 별도의 자동 이득조정 (AGC) 루프가 필요하고, 이는 하드웨어 구현시 시스템의 복잡도와 사용 자원을 증가시킨다. 본 논문에서는 입력 전력에 관계없이 일정한 위상 보정 기능을 수행할 수 있으며 타이밍 복원을 위한 AGC를 동시에 제공할 수 있는 위상 보정 및 진폭 보상 방안을 제안하였다. 제안된 방안은 CORDIC 알고리즘을 사용하여 입력 신호의 위상 및 진폭 정보를 분리하여 각각 처리하며 시스템의 복장도 및 사용 자원을 대폭 절감할 수 있으며, C++ 및 Model Sim을 사용한 모의실험을 통해 본 논문에서 제안한 위상 복원 루프의 동작을 검증하였다.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1999년도 춘계학술대회 논문집
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• pp.88-92
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• 1999

As a part of work to simulate electromagnetic environments for Hardware-In-the-Loop(HIL) simulation, the dynamic trajectory is modeled by the Way-points method and the Event-driven method for the aerial and the naval targets. The simulated results show that the Way-points method and the Event-driven method are appropriate to simulate a low speed and a high speed target respectively.

• 대한산업공학회지
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• 제25권2호
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• pp.282-289
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• 1999

To minimize a real world test of underwater guided vehicle, it is necessary to perform a test on ground by using closed loop test techniques. This paper describes implementation of HILS(Hardware In the Loop Simulation) system for ground test and test methodologies for performance evaluation of a guided weapon. HILS system uses a real time distributed computer and a real time processing technique. Ground test results of underwater vehicle are presented for moving and stationary targets by using HILS system.