• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.4
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• pp.566-572
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• 2013

A microgrid is a small scale power system. The microgrid is operated in two operation modes, the grid-connected mode and the islanded mode. In the islanded mode, the frequency of a microgrid should be maintained constantly. For this, the balance between power supply and power demand during islanded mode should be met. In general, energy storage systems (ESSs) are used to solve power imbalance. In this paper, the frequency control effect of a Lithium-ion battery energy storage system (Li-ion BESS) has been tested on the hardware-in-the loop simulation (HILS) system environment.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.93-97
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• 2005

This paper proposes a design of stepper motor control in microstep driven mode using FPGA (Field Programmable Gate Array) for hardware implementation. The methods to drive stepper motor in microstep excitation mode are to control of the controlling currents in each phase windings of stepper motor with reference signals. These reference signals are used for controlling the current levels, the required variation of current levels with rotor position can be obtained from the ideal linear or sinusoidal approximations to the static torque-displacement ($T-{\theta}$) characteristic curve. In addition, the hardware implementation of stepper motor controller can be designed uses VHDL (Very high speed integrated circuits Hardware Description Language) and synthesis using an Altera FPGA, FLEX10K family, EPF10K20RC240-4 device as target technology and use MAX+PlusII program for overall development. A multi-stack variable-reluctance stepper motor of Sanyo Denki is used in the experiments.

• Korean Journal of Computational Design and Engineering
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• v.11 no.3
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• pp.197-204
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• 2006

This paper introduces a development of an internet based robot on the view of product development for hardware and software convergences. The robot can report moving images of remote places and navigate there autonomously. In addition it can be controlled by remote users through wireless internet. Even the control program for the robot can be updated by the remote users during the regular operation mode. This paper provides a consistent product data model and generic product development processes that can support the development of the robot, a convergence of various hardware and software parts. It also includes discussions and experiences about the development of the convergence product.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1895-1900
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• 2010

In this paper, we propose the hardware architecture of a display converter which is consisted of four functional blocks. The four functional blocks consists of a set of color space converter, de-interacer, video display scaler, and gamma corrector. After the proposed architecture was implemented into hardware, we verified that it operated exactly. The designed hardware has 7,629 LUT and 6,800 Logic Register in Stratix device of Altera and operates in 270 MHz clock frequency.

• ETRI Journal
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• v.45 no.1
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• pp.60-74
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• 2023

Integration of the machine learning (ML) technique in all-optical networks can enhance the effectiveness of resource utilization, quality of service assurances, and scalability in optical networks. All-optical multistage interconnection networks (MINs) are implicitly designed to withstand the increasing highvolume traffic demands at data centers. However, the contention resolution mechanism in MINs becomes a bottleneck in handling such data traffic. In this paper, a select list of ML algorithms replaces the traditional electronic signal processing methods used to resolve contention in MIN. The suitability of these algorithms in improving the performance of the entire network is assessed in terms of injection rate, average latency, and latency distribution. Our findings showed that the ML module is recommended for improving the performance of the network. The improved performance and traffic grooming capabilities of the module are also validated by using a hardware testbed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.9
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• pp.1219-1226
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• 2014

This paper introduces a hardware simulator for the LVRT operation analysis of the grid-tied PMSG wind power system with a power dissipation circuit. The power dissipation circuit, which is composed of chopper and resistor, suppresses the sudden increase of DC-link voltage in the back-to-back converter of the grid-tied PMSG wind power system. The LVRT operation was first analyzed using computer simulations with PSCAD/EMTDC. A wind power simulator including the power dissipation circuit and the fault simulator composed of variac and IGBT were built to analyze the LVRT operation. Various experiments were conducted to verify the effectiveness of the power dissipation circuit for the LVRT operation. The developed hardware simulator can be extensively utilized for the analysis of various LVRT operations of the grid-tied wind power system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.1-8
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• 2023

This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.