• 제목/요약/키워드: Hardware Engineering

검색결과 3,630건 처리시간 0.04초

High Throughput을 위한 블록 암호 알고리즘 ARIA의 하드웨어 설계 및 구현 (Hardware Design and Implementation of Block Encryption Algorithm ARIA for High Throughput)

  • 유흥렬;이선종;손영득
    • 전기전자학회논문지
    • /
    • 제22권1호
    • /
    • pp.104-109
    • /
    • 2018
  • 본 논문에서는 국내 표준으로 제정된 ARIA 알고리즘을 High Throughput을 위한 하드웨어 구조를 제안하고 구현하였다. 치환 계층의 고속 처리를 위하여 ROM table 구성과 라운드 내부의 파이프라인 방식을 이용하며, 12 라운드를 확장된 구조로 설계하여 병렬 특성을 활용 가능한 설계 방법을 제안한다. 본 논문은 VHDL을 이용하여 RTL 레벨로 설계 되었으며, 합성 툴인 Synplify를 이용하였으며, 시뮬레이션을 위해 ModelSim을 이용하였다. 본 논문에서 제시한 하드웨어 구조는 Xilinx VertxeE Series 디바이스를 이용하였으며 68.3 MHz의 주파수 및 674Mbps의 Throughput을 나타낸다.

색상 보정을 위한 CIE1931 색좌표계 변환의 하드웨어 구현 (Hardware implementation of CIE1931 color coordinate system transformation for color correction)

  • 이승민;박상욱;강봉순
    • 전기전자학회논문지
    • /
    • 제24권2호
    • /
    • pp.502-506
    • /
    • 2020
  • 자율주행 기술이 발전함에 따라 물체 인식 기술에 대한 중요도가 높아지고 있다. 물체 인식에 있어서 안개가 낀 날씨는 가시성 및 검출 능력을 저하시키기 때문에 안개 제거 연구가 필요하다. 하지만 안개가 제거된 이미지는 고유의 색상을 제대로 반영하지 못해 검출 오류를 발생시킨다. 본 논문에서는 CIE1931 색 좌표계를 사용해 색상 영역을 확장 또는 축소하여 실세계 색상을 반영하는 알고리즘 및 하드웨어를 제안한다. 또한, 영상 매체의 발달에 맞춰 4K 환경에서 실시간 처리가 가능한 하드웨어를 구현한다. 이 하드웨어는 Verilog로 작성되었으며 SoC 보드를 통해 검증하였다.

예비 서브모듈을 활용한 모듈형 멀티레벨 컨버터의 스위칭 주파수 저감 기법 (Switching Frequency Reduction Method for Modular Multi-level Converter Utilizing Redundancy Sub-module)

  • 이윤석;유승환;최종윤;박용희;한병문;윤영두
    • 전기학회논문지
    • /
    • 제63권12호
    • /
    • pp.1640-1648
    • /
    • 2014
  • This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

An Implementation of the path-finding algorithm for TurtleBot 2 based on low-cost embedded hardware

  • Ingabire, Onesphore;Kim, Minyoung;Lee, Jaeung;Jang, Jong-wook
    • International Journal of Advanced Culture Technology
    • /
    • 제7권4호
    • /
    • pp.313-320
    • /
    • 2019
  • Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

CMOS-IC Implementation of a Pulse-type Hardware Neuron Model with Bipolar Transistors

  • Torita, Kiyoko;Matsuoka, Jun;Sekine, Yoshifumi
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2000년도 ITC-CSCC -2
    • /
    • pp.615-618
    • /
    • 2000
  • A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

  • PDF

실시간 모바일 레이트레이싱 하드웨어를 위한 소프트 쉐도우 생성 기법 (A Soft Shadow Technique for a Real-time Mobile Ray Tracing Hardware)

  • 권혁주;홍덕기;박우찬;이상훈
    • 한국컴퓨터그래픽스학회논문지
    • /
    • 제23권3호
    • /
    • pp.55-64
    • /
    • 2017
  • 본 논문에서는 실시간 모바일 레이트레이싱에서 사실적인 그림자를 생성하기 위한 새로운 그림자 생성 기법을 제시한다. 일반적으로 레이트레이싱에서는 그림자 광선을 샘플링 하여 부드러운 그림자를 생성한다. 지금까지 이런 생성 방법은 처리해야 할 광선의 수를 증가시키기 때문에 성능 저하의 요인이 되어왔다. 제안하는 소프트 쉐도우 생성 기법과 하드웨어 구조는 선택적 그림자 생성과 삼각형 주소 캐싱을 통해 샘플링에 의한 성능 저하를 최소화시킴으로써 이런 문제를 해결하였다. 제안된 하드웨어 구조는 모바일 레이트레이싱 하드웨어에 통합 가능한 수준이며, FPGA상에서 성능 평가 되었다. 평가 결과 제안된 기법의 성능은 4, 8, 그리고 16 샘플에 대해서 이전 기법 대비 평균 40%, 50% 그리고 56% 수준으로 향상 되었으며, 우리는 제안된 하드웨어 구조를 통해 실시간으로 소프트 쉐도우를 생성할 수 있음을 확인하였다.

HEVC 부호기를 위한 효율적인 SAO의 저면적 하드웨어 설계 (Low Area Hardware Design of Efficient SAO for HEVC Encoder)

  • 조현표;류광기
    • 한국정보통신학회논문지
    • /
    • 제19권1호
    • /
    • pp.169-177
    • /
    • 2015
  • 본 논문에서는 HEVC(High Efficiency Video Coding) 부호기를 위한 효율적인 SAO(Sample Adaptive Offset)의 저면적 하드웨어 구조를 제안한다. SAO는 HEVC 영상 압축 표준에서 채택된 새로운 루프 내 필터 기술로서 최적의 오프셋 값들을 화소 단위로 적용하여 영역 내 평균 화소 왜곡을 감소시킨다. 하지만 표준 SAO는 화소 단위 연산을 수행하기 때문에 초고해상도 영상을 처리하기 위해서 많은 연산시간과 연산량을 요구한다. 제안하는 SAO 하드웨어 구조는 SAO의 연산시간을 감소시키기 위해서 한번에 4개의 입력 화소들을 병렬적으로 처리하며, 2단계 파이프라인 구조를 갖는다. 또한 하드웨어 면적을 최소화하기 위해서 휘도 성분과 색차 성분에 대해 단일 구조를 가지며, 하드웨어에 적합한 연산기 및 공통 연산기를 사용한다. 제안하는 SAO 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC $0.13{\mu}m$ CMOS 표준 셀 라이브러리로 합성한 결과 약 190k개의 게이트로 구현되었다. 제안하는 SAO 하드웨어 구조는 200MHz의 동작주파수에서 4K UHD@60fps 영상의 실시간 처리가 가능하며, 최대 250MHz까지 동작 가능하다.

Road-friendliness of Fuzzy Hybrid Control Strategy Based on Hardware-in-the-Loop Simulations

  • Yan, Tian Yi;Li, Qiang;Ren, Kun Ru;Wang, Yu Lin;Zhang, Lu Zou
    • Journal of Biosystems Engineering
    • /
    • 제37권3호
    • /
    • pp.148-154
    • /
    • 2012
  • Purpose: In order to improve road-friendliness of heavy vehicles, a fuzzy hybrid control strategy consisting of a hybrid control strategy and a fuzzy logic control module is proposed. The performance of the proposed strategy should be effectively evaluated using a hardware-in-the-loop (HIL) simulation model of a semi-active suspension system based on the fuzzy hybrid control strategy prior to real vehicle implementations. Methods: A hardware-in-the-loop (HIL) simulation system was synthesized by utilizing a self-developed electronic control unit (ECU), a PCI-1711 multi-functional data acquisition board as well as the previously developed quarter-car simulation model. Road-friendliness of a semi-active suspension system controlled by the proposed control strategy was simulated via the HIL system using Dynamic Load Coefficient (DLC) and Dynamic Load Stress Factor (DLSF) criteria. Results: Compared to a passive suspension, a semi-active suspension system based on the fuzzy hybrid control strategy reduced the DLC and DLSF values. Conclusions: The proposed control strategy of semi-active suspension systems can be employed to improve road-friendliness of road vehicles.

곱셈기가 제거된 의료 초음파 신호처리용 프로그래머블 FIR 필터 구현을 위한 수정된 SaA 구조 (A Modified SaA Architecture for the Implementation of a Multiplierless Programmable FIR Filter for Medical Ultrasound Signal Processing)

  • 한호산;송재희;김학현;고방영;송태경
    • 대한의용생체공학회:의공학회지
    • /
    • 제28권3호
    • /
    • pp.423-428
    • /
    • 2007
  • Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

승용 자동차 조종장치 스테레오타입 조사를 위한 설문조사와 실물 시뮬레이션 방법 비교 (Comparison of Paper-Pencil and Hardware Tests for Investigating Stereotypes for Controls of Passenger Cars)

  • 기도형
    • 대한안전경영과학회지
    • /
    • 제15권2호
    • /
    • pp.63-69
    • /
    • 2013
  • The purposes of this study are to survey stereotypes of control-display relationships for seven principal controls in passenger cars using the paper-pencil and hardware tests, and to examine stereotype strength of the paper-pencil test through comparing the stereotypes for the controls derived by the two methods. Ninety two and 60 college-aged students participated in the paper-pencil test and the real car simulation of the hardware test, respectively. There are dominant motion-directions for all controls in the paper-pencil test, while in the hardware test, there are dominant motion-directions for six controls including head light, high beam, door window, ignition key, door key and door lock controls. The stereotypes of motion-directions for six controls obtained by the paper-pencil test were the same as or similar to those by the hardware test. It was inferred from this that the congruence of the stereotypes by the two methods might be attributed to two simple motion-direction principles of 'clockwise for increase' and 'upward for increase.' Although it is known that the hardware test would be best for obtaining accurate stereotypes between controls and displays, this study implies that if the paper-pencil test is well designed, the paper-pencil test can produce the same results as the hardware test at low cost and without consuming time.