• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2232-2239
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• 2016

IoT industry has been highlighted in the domestic and foreign country. Since most IoT systems operate separate servers in Internet to control IoT hardwares, there exists the possibility of security problems. Also, IoT systems in markets use their own hardware controllers and devices. As a result, there are many limitations in adding new sensors or devices and using applications to access hardware controllers. To solve these problems, we have developed a novel IoT hardware control system based on a mobile messenger. For the security, we have adopted a secure mobile messenger, Telegram, which has its own security protection. Also, it can improve the easy of the usage without any installation of specific applications. For the enhancement of the system accessibility, the proposed IoT system supports various network protocols. As a result, there are many possibility to include various functions in the system. Finally, our IoT system can analyze the collected information from sensors to provide useful information to the users. Through the experiment, we show that the proposed IoT system can perform well.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.740-743
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• 2015

The increasing complexity of integrated circuits and IP-based hardware designs have created the risk of hardware Trojans. This paper introduces a new type of threat, the coherence-exploiting hardware Trojan. This Trojan can be maliciously implanted in master components in a system, and continuously injects memory read transactions on to bus or main interconnect. The injected traffic forces the eviction of cache lines, taking advantage of cache coherence protocols. This type of Trojans insidiously slows down the system performance, incurring Denial-of-Service (DoS) attack. We used Xilinx Zynq-7000 device to implement and evaluate the coherence-exploiting Trojan. The malicious traffic was injected through the AXI ACP interface in Zynq-7000. Then, we collected the L2 cache eviction statistics with performance counters. The experiment results reveal the severe threats of the Trojan to the system performance.

• Journal of Broadcast Engineering
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• v.26 no.7
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• pp.855-861
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• 2021

Neural Architecture Search (NAS) is cutting-edge technology in the machine learning community. NAS Without Training (NASWOT) recently has been proposed to tackle the high demand of computational resources in NAS by leveraging some indicators to predict the performance of architectures before training. The advantage of these indicators is that they do not require any training. Thus, NASWOT reduces the searching time and computational cost significantly. However, NASWOT only considers high-performing networks which does not guarantee a fast inference speed on hardware devices. In this paper, we propose a multi objectives reward function, which considers the network's latency and the predicted performance, and incorporate it into the Reinforcement Learning approach to search for the best networks with low latency. Unlike other methods, which use FLOPs to measure the latency that does not reflect the actual latency, we obtain the network's latency from the hardware NAS bench. We conduct extensive experiments on NAS-Bench-201 using CIFAR-10, CIFAR-100, and ImageNet-16-120 datasets, and show that the proposed method is capable of generating the best network under latency constrained without training subnetworks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• International Journal of Aeronautical and Space Sciences
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• v.9 no.2
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• pp.121-128
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• 2008

Modularized GPS software defined radio (SDR) has many advantages of applying and modifying algorithm. Hardware based GPS receiver uses many hardware parts (such as RF front, correlators, CPU and other peripherals) that process tracked signal and navigation data to calculate user position, while SDR uses software modules, which run on general purpose CPU platform or embedded DSP. SDR does not have to change hardware part and is not limited by hardware capability when new processing algorithm is applied. The weakness of SDR is that software correlation takes lots of processing time. However, in these days the evolution of processing power of MPU and DSP leads the competitiveness of SDR against the hardware GPS receiver. This paper shows a study of modulization of GPS software platform and it presents development of the GNSS software platform using MATLAB Simulink™. We focus on post processing SDR platform which is usually adapted in research area. The main functions of SDR are GPS signal acquisition, signal tracking, decoding navigation data and calculating stand alone user position from stored data that was down converted and sampled intermediate frequency (IF) data. Each module of SDR platform is categorized by function for applicability for applying for other frequency and GPS signal easily. The developed software platform is tested using stored data which is down-converted and sampled IF data file. The test results present that the software platform calculates user position properly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1688-1696
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• 2020

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.819-824
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• 2021

As technologies related to image processing such as autonomous driving and CCTV develop, fog removal algorithms using a single image are being studied to improve the problem of image distortion. As a method of predicting fog density, there is a method of estimating the depth of an image by generating a depth map, and various fog features may be used as training data of the depth map. In addition, it is essential to implement a hardware capable of processing high-definition images in real time in order to apply the fog removal algorithm to actual technologies. In this paper, we implement NLCV (Normalize Local Coefficient of Variation), a feature of fog based on coefficient of variation, in hardware. The proposed hardware is an FPGA implementation of Xilinx's xczu7ev-2ffvc1156 as a target device. As a result of synthesis through the Vivado program, it has a maximum operating frequency of 479.616MHz and shows that real-time processing is possible in 4K UHD environment.

• Journal of IKEEE
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• v.28 no.3
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• pp.321-328
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• 2024

The growth of the multimedia industry has led to the advent of digital devices utilizing images of varying resolutions. Accordingly, it is essential to adapt the resolution of the source image to match with the resolutions of the target digital device, while ensuring that the quality of the input image is preserved throughout this process. In this paper, we propose the implementation of a hardware system that performs image scaling using interpolation algorithms. The bicubic interpolation algorithm is employed as the interpolation algorithm, as it produces the highest quality image among the three most common methods. Each interpolated axis in the image can be operated independently to achieve asymmetric scaling in any desired ratio. The hardware of the proposed scaler satisfies real-time processing and is implemented with less memory resources than the previously studied hardware using the time allocation method, showing that it is a suitable structure for the hardware of the scaler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.643-645
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• 2011

We analysed a hardware design issues, which is strong, compact and efficient. Due to its low area constraints, primitive based on hardware is especially suited for RFID (Radio Frequency Identification) devices. primitive is based on the classical DES (Data Encryption Standard) design. This approach makes it possible to considerably decrease chip size requirements.