• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.10
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• pp.53-59
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• 2011

In recent years, mobile communication service is used extensively as a larger service area for the maintenance of quality of service required by the expansion of service areas and As the ever-increasing role in relays, and the location is relatively easy to install and less constrained costs, operating cost savings in terms of ICS(Interference Cancellation System) repeaters are required. However, an adaptive algorithm that is applied when updating the filter due to the increase in volume of operations increase the complexity of hardware implementation is fraught with many difficulties. In this paper, if there is a path that feedback. ICS repeater utilizing baseband signal processing for the removal of interfering signals from the feedback operation, significantly reducing the amount of reducing hardware complexity Complex Singed Signed LMS adaption algorithm is proposed. Proposed algorithm for evaluating the performance of Static channel WCDMA signal environment for the ICS, the results of the simulation algorithm, convergence speed and better performance in therms of convergence errors that are required through the implementation of the operation greatly reduces the amount of hardware complexity able to reduce the effect was visible.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.299-306
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• 2003

This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. Embedded system re-engineering is defined as a development task of meeting performance requirements newly imposed on a system after its hardware and software have been fully implemented. The performance requirements nay include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. The inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new real-time throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck precesses in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance staling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirement. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1195-1211
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• 2016

The emerging video coding standard High Efficiency Video Coding (HEVC) has shown almost 40% bit-rate reduction over the state-of-the-art Advanced Video Coding (AVC) standard but at about 40% computational complexity overhead. The main reason for HEVC computational complexity is the inter prediction that accounts for 60%-70% of the whole encoding time. In this paper, we propose several fast coding unit (CU) encoding schemes based on the Merge mode and motion estimation information to reduce the computational complexity caused by the HEVC inter prediction. Firstly, an early Merge mode decision method based on motion estimation (EMD) is proposed for each CU size. Then, a Merge mode based early termination method (MET) is developed to determine the CU size at an early stage. To provide a better balance between computational complexity and coding efficiency, several fast CU encoding schemes are surveyed according to the rate-distortion-complexity characteristics of EMD and MET methods as a function of CU sizes. These fast CU encoding schemes can be seamlessly incorporated in the existing control structures of the HEVC encoder without limiting its potential parallelization and hardware acceleration. Experimental results demonstrate that the proposed schemes achieve 19%-46% computational complexity reduction over the HEVC test model reference software, HM 16.4, at a cost of 0.2%-2.4% bit-rate increases under the random access coding configuration. The respective values under the low-delay B coding configuration are 17%-43% and 0.1%-1.2%.

• ETRI Journal
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• v.25 no.6
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• pp.489-502
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• 2003

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.1
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• pp.118-128
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• 2017

In this study, we propose a real time inertial navigation system/global positioning system (INS/GPS) integrated smoothing algorithm based on an extended Kalman filter (EKF) and a position damping loop (PDL) for synthetic aperture radar (SAR). Integrated navigation algorithms usually induce discontinuities due to error correction update by the Kalman filter, which are as detrimental to the performance of SAR as the relative position error. The proposed smoothing algorithm suppresses these discontinuities and also reduces the relative position error in real time. An EKF estimates the navigation errors and sensor biases, and all the errors except for the position error are corrected directly and instantly. A PDL activated during SAR operation period imposes damping effects on the position error estimates, where the estimated position error is corrected smoothly and gradually, which contributes to the real time smoothing and small relative position errors. The residual errors are re-estimated by the EKF to maintain the estimation performance and the stability of the overall loop. The performance improvements were confirmed by Monte Carlo simulations. The simulation results showed that the discontinuities were reduced by 99.8% and the relative position error by 48% compared with a conventional EKF without a smoothing loop, thereby satisfying the basic performance requirements for SAR operation. The proposed algorithm may be applicable to low cost SAR systems which use a conventional INS/GPS without changing their hardware configurations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.5
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• pp.55-63
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• 2013

In cognitive radio networks, acquirement of position information of primary user is very important to secondary network since localization information of primary users can be utilized for improving the spectrum efficiency of secondary network and for avoiding harmful interference to primary users by using proper power control. Among various location methods, Received Signal Strength (RSS)-based localization has been widely used for distance measurements in the location detection process despite its inherent inaccuracy because it can be easily implemented without any additional hardware cost. In the RSS-based localization, the distance is measured by the received signal strength, and distance error can be caused by many factors such as fading, shadowing and obstacle between two nodes. In the paper, therefore we propose a localization scheme based on estimation of path-loss exponent to localize the location of primary users more accurately. Through simulations, it is shown that the proposed scheme can provide less localization error and interference rate to primary users than other schemes.

• The KIPS Transactions:PartC
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• v.15C no.1
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• pp.31-36
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• 2008

The clock frequency difference of sensor nodes is one of main parameters in TOF estimation and affect to degrade ranging algorithms to estimate positions of mobile nodes in wireless sensor networks. The specification of IEEE802.15.4a describes asynchronous TWR and SDS-TWR insensitive to frequency difference without any additional network synchronization. But the TWR and SDS-TWR can not eliminate sufficiently the effect of frequency difference of node pair, packet processing delay and its difference. Especially use of low cost oscillator with wide range offset, sensor node with different hardware and software can make the positioning errors worse. We propose an estimation method of frequency differences, and apply the measured frequency differences to TWR and SDS-TWR. We evaluate the performance of the proposed algorithm with simulation, and make certain that the proposed method enhances the performance of existing algorithms with positioning errors less than 25 cm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.215-217
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• 2014

A system architecture design relying only on the experience of its designer varies in quality in line with the designer's personal experience and knowledge ability. Likewise, a wrong estimation of hardware capacity ends up in waste of resources. In practice, a range of post-hoc monitoring tools are in operation, without providing any method for estimating and reflecting the performance at an early stage of architecture design. Provided capacity requirement is estimated in advance with simulation at the stage of design, the system capacity ends up in waste of resources. In practice, a range of post-hoc monitoring tools are in operation, without providing any method for estimating and reflecting the performance at an early stage of architecture design. Provided capacity requirement is estimated in advance with simulation at the stage of design, the system performance requirement can be met with a minimal cost while the waste of resources can be reduced to a great extent. In this context, the present study develops a pilot simulation model for hardware architecture design and then verifies its validity in an experiment. If the error rate falls within a permissible range in the experiment, the simulation model may be considered to reflect well the characteristics of real-life information system architecture.

• International Journal of Computer Science & Network Security
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• v.24 no.4
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• pp.163-169
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• 2024

India is a developing nation and has come with comprehensive way in modernizing its reducing poverty, economy and rising living standards for an outsized fragment of its residents. The STEM (Science, Technology, Engineering, and Mathematics) education plays an important role in it. STEM is an educational curriculum that emphasis on the subjects of "science, technology, engineering, and mathematics". In traditional education scenario, these subjects are taught independently, but according to the educational philosophy of STEM that teaches these subjects together in project-based lessons. STEM helps the students in his holistic development. Youth unemployment is the biggest concern due to lack of adequate skills. There is a huge skill gap behind jobless engineers and the question arises how we can prepare engineers for a better tomorrow? Now a day's Industry 4.0 is a new fourth industrial revolution which is an intelligent networking of machines and processes for industry through ICT. It is based upon the usage of cyber-physical systems and Internet of Things (IoT). Industrial revolution does not influence only production but also educational system as well. IoT in academics is a new revolution to the Internet technology, which introduced "Smartness" in the entire IT infrastructure. To improve socio-economic status of the India students must equipped with 21st century digital skills and Universities, colleges must provide individual learning kits to their students which can help them in enhancing their productivity and learning outcomes. The major goal of this paper is to present a low cost, effective learning mechanism for STEM implementation using Raspberry Pi 3+ model (Single board computer) and Node Red open source visual programming tool which is developed by IBM for wiring hardware devices together. These tools are broadly used to provide hands on experience on IoT fundamentals during teaching and learning. This paper elaborates the appropriateness and the practicality of these concepts via an example by implementing a user interface (UI) and Dashboard in Node-RED where dashboard palette is used for demonstration with switch, slider, gauge and Raspberry pi palette is used to connect with GPIO pins present on Raspberry pi board. An LED light is connected with a GPIO pin as an output pin. In this experiment, it is shown that the Node-Red dashboard is accessing on Raspberry pi and via Smartphone as well. In the final step results are shown in an elaborate manner. Conversely, inadequate Programming skills in students are the biggest challenge because without good programming skills there would be no pioneers in engineering, robotics and other areas. Coding plays an important role to increase the level of knowledge on a wide scale and to encourage the interest of students in coding. Today Python language which is Open source and most demanding languages in the industry in order to know data science and algorithms, understanding computer science would not be possible without science, technology, engineering and math. In this paper a small experiment is also done with an LED light via writing source code in python. These tiny experiments are really helpful to encourage the students and give play way to learn these advance technologies. The cost estimation is presented in tabular form for per learning kit provided to the students for Hands on experiments. Some Popular In addition, some Open source tools for experimenting with IoT Technology are described. Students can enrich their knowledge by doing lots of experiments with these freely available software's and this low cost hardware in labs or learning kits provided to them.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.