• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.1
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• pp.7-13
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• 2004

Previously, in order to send information from the local controller to the display board, the hardware or software had to be handled and run through 3-phases, which include the PC-card or PC-add Board, I/F card and Sub board. This study will attempt to design a board that handles information by connecting the USB port of the PC directly to the Sub board. In addition, an MPU will be attached to the previously complex hardware circuit to design a software drive engine module, which allows for the development of new products by modifying only the software engine and not the hardware.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.111-111
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• 2000

The research of network system, being used to reduce automotive wiring harness, is reaching to the development of by-wire system. It is by-wire system that apply IVN(In-Vehicle-Network) to steering, braking system, and it has the advantage of mass-decreasing, easy to diagnose fault and so on. But until now, many developed device can't satisfied with reliability that system have ever had. So redundancy of each network module, i.e., It is only way to make backup module. This paper researches development of network module and redundancy management of backup module when error occurred for implementation of brake-by-wire system.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.396-401
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• 2009

This paper describes the improvements made on hardware and software of the remote controller for realistic contents. The controller can provide vibrotactile feedback which uses both of a voice-coil actuator and a vibration motor. A vision tracking system for the 3D position of the controller is optimized with respect to the marker size and the camera parameters. We also present the improvements of motion recognition due to the effective motion segmentation and the fusion of vision and acceleration data. We apply the developed controller to realistic contents and validate its usability.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1978-1987
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• 2014

Power requirement to the induction heating system varies during the heating process. A closed loop control is required to have a smooth control over the power. In this work, a constant frequency pulse density modulation based power tracking control scheme for domestic induction heating system is developed using the Fuzzy Logic Controller. In the conventional power modulation schemes, the switching losses increase with the change in the load. The proposed pulse density modulation scheme maintains minimum switching losses for the entire load range. This scheme is implemented for the class-D series resonant inverter system. Fuzzy logic controller based power tracking control scheme is developed for domestic induction heating power supply for various power settings. The open loop and closed loop simulation studies are done using the MATLAB/Simulink simulation tool. The control logic is implemented in hardware using the PIC16F877A microcontroller. Fuzzy controller tracks the set power by changing the pulse density of the gate pulses applied to the inverter. The results obtained are used to know the effectiveness of the fuzzy logic controller to achieve the set power.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1972-1977
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• 2005

In this work, an inverse dynamic control method is developed to enhance tracking performance of industrial robots, which effectively deal with the nonlinear dynamic interferential forces. In general, the DFF (Dynamic Feed-Forward) controller and the CTM (Computed-Torque Method) controller are used for dynamic control for industrial robots. We study on the practical issues for implementing these inverse dynamic controllers via simulations and experiments. We develop the dynamic models in two different ways. One is a model designed through Newton-Euler method for real time computation and the other is a model designed through SimMechanics for evaluating the developed controller via simulations. We evaluate the nominal performance and robustness of the controller via simulations and experiments using serial 4-DOF HyRoHILS (Hyundai Robot Hardware-In-the-Loop Simulation) system. The results show that the inverse dynamic controller is effective and practically useful for a real control structure.

• Journal of Drive and Control
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• v.9 no.4
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• pp.58-61
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• 2012

The customers who used the hydroulic system desire the product that has more detailed specification quickly during the industrial technology is developed. Every researcher try to reduce the developed period and to satisfy the customers' desire. Lot's of simulation software and hardware already was used to be satisfied those purpose. But these kind of equipment need a lot of cost to set up and technical knowledge to drive that system. This paper concerns about analog PID controller that can be assembled with a few resistor, condenser and optional amplifier and doesn't need technical knowledge to drive. At the first, the plant was modeled mathematically to design the analog PID controller's circuit. After that, PID controller's parameter was selected by customers' desire. Finally, the analog PID controller's circuit was assembled from the control law. The circuit's availability was confirmed by step response test in the controlled system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.445-452
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• 2010

In this paper, an attempt has been made to design the controller applicable for H.264 level3 encoder of baseline profile on full hardware basis. The designed controller module first stores the images supplied from CMOS Image Sensor(CIS) at main memory, and then reads or stores the image data in macroblock unit according to encoder operation. The timing cycle of the DMA controller required to process a macroblock is 478 cycles. In order to verify the our design, reference-C encoder, which is compatible to JM 9.4, is developed and the designed controller is verified by using the test vector generated from the reference C code. The number of cycle in the designed DMA controller is reduced by 40% compared with the cycle of using Xilinx MIG.