• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.4
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• pp.175-182
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• 2000

The back-light inverter used in the laptop computer is designed in this paper. It has been difficult for electromagnetic transformer to enhance the efficiency and compact profile of the inverter. In this paper, (1) the piezoelectric transformer (PT) is used for reducing the loss; (2) the volumes of core and winding coil are used in electromagnetic transformer, and (3) the half-bridge series parallel resonant circuit is used in the driver of the inverter. The modified PT for this paper and the equivalent circuit are supported by the simulation program. The result of the experiment shows more than 91% improvement in terms of the efficiency.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.8
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• pp.417-425
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• 1999

This paper presents an effective control scheme with the voltage-fed half-bridge series resonant inverter for induction heating system, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuits. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching) irrespective of sensitive load parameter variations, specially in the non-magnetic materials as well as power regulation. The detail operation principle and the characteristics of inverter system with the proposed control scheme are described and its validity is verified by the simulation and the experimental results for a prototype induction cooking system rated at 1.2kW.

• Journal of Power Electronics
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• v.12 no.5
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• pp.699-707
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• 2012

This paper proposes a single-stage half-bridge electronic ballast with a high power factor using only a single coupled inductor. Compared to conventional high power factor electronic ballasts, the proposed ballast is a simpler circuit with a low cost and a high reliability. The proposed ballast is made up of a power-factor-correction (PFC) circuit and a self-oscillating class-D inverter. The PFC and inverter stages of the proposed ballast are simplified by sharing only a single coupled inductor and two common switches. The proposed PFC circuit can achieve a high power factor and low voltage stresses of the switches. A saturable transformer in the self-oscillating class-D inverter determines the switching frequency of the ballast. Experimental results obtained on a 30W fluorescent lamp are discussed.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2234-2236
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• 1997

The SIT, a Static Induction Transistor, is a semiconductor switch that is also called the power junction field-effect transistor (power JFET). Its characteristics are similar to a MOSFET except that its power level is higher and its maximum frequency of operation is lower. The normal method to protect against internal circuit transients of the form of di/dt or dv/dt is the use of snubber circuits. However, the limits of di/dt and dv/dt are high enough for the SIT that it is possible to operate without snubber circuits. SITs can be connected in parallel in order to cope with higher load currents that the value of an individual device rating. The purpose of this study is to investigate the parallel operation of SITs. In this experiment, we used a half-bridge inverter, the output of inverter is up to almost 1MHz and 2kW. Experimental results show that the operation of parallel connected SITs are facilitated individually good current sharing. The reason is the positive temperature coefficient of resistance of the SIT.

• Journal of Power Electronics
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• v.18 no.1
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• pp.116-128
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• 2018

Conventionally, in order to reduce the ac components of the dc-link capacitors of the two-level Half-Bridge Voltage Source Inverter (HB-VSI), high dc-link capacitances are required. This necessitates the employment of short-lifetime and bulky electrolytic capacitors. In this paper, an analysis for the performance of low dc-link capacitances-based HB-VSI is presented to elucidate its ability to generate an enhanced fundamental output voltage magnitude without increasing the voltage rating of the involved switches. This feature is constrained by the load displacement factor. The introduced enhancement is due to the ac components of the capacitors' voltages. The presented approach can be employed for multi-phase systems through using multi single-phase HB-VSI(s). Mathematical analysis of the proposed approach is presented in this paper. To ensure a successful operation of the proposed approach, a closed loop current controller is examined. An expression for the critical dc-link capacitance, which is the lowest dc-link capacitance that can be employed for unipolar capacitors' voltages, is derived. Finally, simulation and experimental results are presented to validate the proposed claims.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.260-264
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• 2004

In this paper the novel converter topology for the switched reluctance motor drives is proposed, which is composed of the minimum switch per phase and is connected to the single-phase voltage inverter for ac voltage source. The proposed converter topology is divided into two types according to the voltage source inverter of half bridge type and full bridge type. Proposed converters of two types are proposed, analyzed and compared with each other. The SRM using proposed converter maintain the hi인 efficiency though the power switches are reduced.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.443-450
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• 2000

A PWM inverter for an induction motor often has a problem with a high frequency leakage current that flows through stray capacitors between stator windings and a motor frame to ground. This paper proposes a new type of Active Common Mode Voltage Canceler circuit for the reduction of common mode voltage and high frequency leakage current generated by the PWM VSI-fed induction motor drives. The compensating voltage applied by the common made voltage canceler has the same amplitude as, hut the opposite polarity to, the common mode voltage by PWM Inverter. Therefore, common mode voltage and high frequency leakage current can be canceled. The proposed circuit consists of four-level half-bridge inverter and common-mode transformer. Simulated and experimental results show that common mode voltage canceler makes significant contributions to reducing a high frequency leakage current.

• Journal of Power Electronics
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• v.9 no.4
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.1
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• pp.47-53
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• 2006

In this paper, a simple scheme compensating for the effect of dc-link ripple voltages on output voltage of two-leg and three-phase PWM inverters is proposed, where single-phase half-bridge PWM convertor and two-leg inverter are used. The voltage at neutral point of the dc-link is controlled so that the upper-half of do-link voltage is equal to the lower-half voltage in average concept. However, the effect of the do-link ripple voltage results in the inverter output voltage and current distortion. This effect can be eliminated by introducing a compensation voltage in switching time calculation. Also, the inverter dead time should be compensated for sinusoidal output waveform. The proposed scheme has been verified by experimental results which were obtained from the V/F constant operation of the induction motor fed by two-leg inverter.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.57-66
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• 1993

This research proposes a high frequency series resonant inverter consisting of equivalent half - bridge model in combination with two L-C linked full-bridge inverter circuits using MOSFET. As a output power control strategy, the sequential gate control method is applied. Also, analysis of operating MODE and state equation is described. From the computer simulation results, the inverters and devices can be shared properly voltage and current rating of the system in accordance with series and parallel operations. And it is confirmed that the proposed system has very stable performance.