• Title/Summary/Keyword: HI layer

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Fabrication and Operating Properties of Nb Silicide-coated Si-tip Field Emitter Arrays (니오비움 실리사이드가 코팅된 실리콘 팁 전계 방출 소자의 제조 및 동작 특성)

  • Ju, Byeong-Kwon;Park, Jae-Seok;Lee, Sangjo;Kim, Hoon;Lee, Yun-Hi;Oh, Myung-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.7
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    • pp.521-524
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    • 1999
  • Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

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Improvement of NBTI Lifetime Utilizing Optimized BEOL Process Flow (새로운 BEOL 공정을 이용한 NBTI 수명시간 개선)

  • Ho Won-Joon;Han In-Shik;Lee Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.9-14
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    • 2006
  • The dependence of NBTI lifetime on the BEOL processes such as sintering gas type and passivation layer has been characterized in depth. Then, optimized BEOL process scheme is proposed to improve NBTI lifetime. NBTI showed degradation due to the plasma enhanced nitride (PE-SiN) passivation film and $H_2$ sintering anneal. Then, new process scheme of $N_2$ annealing instead of $H_2$ annealing prior to PE-SiN deposition is proposed. The proposed BEOL process flow showed that NBTI lifetime can be improved a lot without degradation of device performance and NMOS hot carrier reliability.

Fabrication of a fast Switching Thyristor by Proton Irradiation Method (양성자 조사법에 의한 고속스위칭 사이리스터의 제조)

  • Kim, Eun-Dong;Zhang, Changli;Kim, Sang-Cheol;Kim, Nam-Kyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.12
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    • pp.1264-1270
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    • 2004
  • A fast switching thyristor with a superior trade-off property between the on-state voltage drop and the turn-off time could be fabricated by the proton irradiation method. After making symmetric thyristor dies with a voltage rating of 1,600 V from 350 $\mu$m thickness of 60 $\Omega$ㆍcm NTD-Si wafer and 200 $\mu$m width of n-base drift layer, the local carrier lifetime control by the proton irradiation was performed with help of the HI-13 tandem accelerator in China. The thyristor samples irradiated with 4.7 MeV proton beam showed a superior trade-off relationship of $V_{TM}$ = 1.55 V and $t_{q}$ = 15 $\mu$s attributed to a very narrow layer of short carrier lifetime(~1 $\mu$s) in the middle of its n-base drift region. To explain the small increase of $V_{TM}$ , we will introduce the effect of carrier compensation at the low carrier lifetime region by the diffusion current.ffusion current.t.

Field Emission properties of Porous Polycrystalline silicon Nano-Structure (다결정 다공질 실리콘 나노구조의 전계 방출 특성)

  • Lee, Joo-Won;Kim, Hoon;Park, Jong-Won;Lee, Yun-Hi;Jang, Jin;Ju, Byeong-Kwon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.04b
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    • pp.69-72
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    • 2002
  • We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^{2}$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.

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Thermal Stability Improvement of Ni-Germanide Using Ni-N(1%) for Nano Scale Ge-MOSFET Technology (나노급 Ge-MOSFET를 위한 Ni-N(1%)을 이용한 Ni-germanide의 열 안정성 개선)

  • Yim, Kyeong-Yeon;Park, Kee-Young;Zhang, Ying-Ying;Li, Shi-Guang;Zhong, Zhun;Jung, Soon-Yen;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.17-18
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    • 2008
  • In this paper, 1%-nitrogen doped Nickel was used for improvement of thermal stability of Ni-Germanide. Proposed Ni-N(1%)/TiN structure has shown better thermal stability, sheet resistance and less agglomeration characteristic than pure Ni/TiN structure. During the germanidation process, it is believed that the nitrogen atoms in the deposited nickel layer can suppress the agglomeration of Ni germanide by retarding the diffusion of Ni atoms toward silicon layer, hence improve the thermal stability of Ni-germanide.

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Study on the Fabrication and Evaluation of the MEMS Based Curved Beam Air Flowmeter for the Vehicle Applications (MEMS 기반의 차량용 휨형 유속센서의 제작 및 특성 연구)

  • Park, Cheol Min;Choi, Dae Keun;Lee, Sang Hoon
    • Journal of Sensor Science and Technology
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    • v.25 no.2
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    • pp.116-123
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    • 2016
  • This paper presents the fabrication and evaluation of the novel drag force type air flowmeter using MEMS technologies for the vehicle applications. To obtain the air drag force, the flowmeter utilized the curved beam structure, which was realized by the difference of residual stress between the silicon oxide layer and the silicon nitride layer. The paddle structure was applied for the maximum air drag force, and the dual-beam was adapted to prevent distortion. The basic experiments were performed in the wind tunnel, and the stable outputs were obtained. The device was applied to the internal combustion engine, and the results were compared with the HI-DS output where the convection thermal flowmeter was used as the reference sensor. The results indicated that the comparable resolutions and response times were obtained under the various engine speeds.

A Stacked Polusilicon Structure by Nitridation in N2 Atmosphere for Nano-scale CMOSFETs (나노 CMOS 소자 적용을 위한 질소 분위기에서 형성된 질화막을 이용한 폴리실리콘 적층 구조)

  • Ho, Won-Joon;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.11
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    • pp.1001-1006
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    • 2005
  • A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

Study of Ni-germano Silicide Thermal Stability for Nano-scale CMOS Technology (Nano-scale CMOS를 위한 Ni-germano Silicide의 열 안정성 연구)

  • Huang, Bin-Feng;Oh, Soon-Young;Yun, Jang-Gn;Kim, Yong-Jin;Ji, Hee-Hwan;Kim, Yong-Goo;Wang, Jin-Suk;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.11
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    • pp.1149-1155
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    • 2004
  • In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.

Fabrication of a Fast Switching Thyristor by Proton Irradiation (양성자 조사법에 의한 고속스위칭 사이리스터의 제조)

  • Kim, Eun-Dong;Zhang, Chang-Li;Kim, Sang-Cheol;Kim, Nam-Gyun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.271-275
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    • 2004
  • A fast switching thyristor with a superior trade-off property between the on-state voltage drop and the turn-off time could be fabricated by the proton irradiation method. After fabricating symmetric thyristor dies with a voltage rating of 1,600V from $350{\mu}m$ thickness of $60{\Omega}cm$ NTD-Si wafer and $200{\mu}m$ width of N-base drift layer, the local carrier lifetime control by the proton irradiation was performed with help of the HI-13 tandem accelerator in China. The thyristor samples irradiated with 4.7MeV proton beam showed a superior trade-off relationship of $V_{TM}=1.55V\;and\;t_q=15{\mu}s$ attributed to a very narrow layer of short carrier lifetime(${\sim}1{\mu}s$) in the middle of its N-base drift region. To explain the small increase of $V_{TM}$, we will introduce the effect of carrier compensation by the diffusion current at the low carrier lifetime region.

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Investigation of Device Characteristics on the Mechanical Film Stress of Contact Etch Stop Layer in Nano-Scale CMOSFET (Nano-Scale CMOSFET에서 Contact Etch Stop Layer의 Mechanical Film Stress에 대한 소자특성 분석)

  • Na, Min-Ki;Han, In-Shik;Choi, Won-Ho;Kwon, Hyuk-Min;Ji, Hee-Hwan;Park, Sung-Hyung;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.57-63
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    • 2008
  • In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.