• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.114-124
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• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• Journal of IKEEE
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• v.20 no.4
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• pp.435-438
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• 2016

HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.224-237
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• 2015

In this paper, we introduce the fast decoding method with the SIMD (Single Instruction Multiple Data) instructions for HEVC RExt (High Efficiency Video Coding Range Extensions). Several tools of HEVC RExt such as intra prediction, interpolation, inverse-quantization, inverse-transform, and clipping modules can be classified as the proper modules for applying the SIMD instructions. In consideration of bit-depth increasement of RExt, intra prediction, interpolation, inverse-quantization, inverse-transform, and clipping modules are accelerated by SSE (Streaming SIMD Extension) instructions. In addition, we propose effective implementations for interpolation filter, inverse-quantization, and clipping modules by utilizing a set of AVX2 (Advanced Vector eXtension 2) instructions that can use 256 bits register. The evaluation of the proposed methods were performed on the private HEVC RExt decoder developed based on HM 16.0. The experimental results show that the developed RExt decoder reduces 12% average decoding time, compared with the conventional sequential method.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.171-182
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• 2015

HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of IKEEE
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• v.21 no.3
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• pp.280-283
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• 2017

HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.