• Transactions on Electrical and Electronic Materials
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• v.3 no.4
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• pp.1-4
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• 2002

As the application of semiconductor chips into electronics increases, it requires more complete integration, which results in higher performance. And it needs minimization in device design for cost saving of manufacture. Therefore oxide gap fill has become one of the major issues in sub-micron devices. Currently HDP (High-Density Plasma) CVD system is widely used in IMD (Inter Metal Dielectric) to fill narrower space between metal lines. However, HDP-CVD system has some potential problems such as plasma charging damage, metal damage and etc. Therefore, we will introduce about one of via resistance failure by metal damage and a preventive method in this paper.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1398-1399
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• 2006

현재 상용화된 OLED 소자는 최대 단점인 수분 취약성의 원인으로 top emission과 flexible 타입으로 제조되는데 장애가 되고 있다. 따라서 top emission 방식과 flexible한 소자를 실현하기 위해 수분 및 산소 침투를 방지하기 위한 유전체 막의 실험이 진행되고 있는데, 본 실험에서는 기존의 PECVD보다 plasma의 density가 높은 HDP(High Density Plasma)-CVD를 사용해 SiOx 및 SiNx 유전체 film을 증착하였고 MOCON 테스트를 통한 수분침투 방지막으로써의 가능성을 검증하였다.

• Journal of the Korean Ceramic Society
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• v.39 no.6
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• pp.570-575
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• 2002

The present tendency of electrical and electronics is concentrated on MEMS devices for advantage of miniaturization, intergration, low electric power and low cost. Therefore it is essential that high aspect ratio and high etch rate by HDP technology development, so that silicon deep trench etching reactions was studied by ICP equipment. Deep trench etching of silicon was investigated as function of platen power, etch step time of etch/passivation cycle time and SF$\_$6/:C$_4$F$\_$8/ flow rate. Their effects on etch profile, scallops, etch rate, uniformity and selectivity were also studied.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.183-183
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• 2010

최근 고밀도 플라즈마(High Density Plasma, HDP)를 이용하여 STI (shallow trench Isolation) 공정에 사용하기 위한 높은 종횡비를 가지는 갭을 공극 없이 절연물질로 채우는 HDP CVD 법이 개발되어 사용되고 있으며, HDP 공정에서는 그 증착 과정 중에 스퍼터링(Sputtering)에 의한 식각이 동시에 발생하기 때문에 높은 종횡비를 가지는 갭을 공극 없이 채우는 것이 가능하게 되었다. 이러한 특성을 이용하여 HDP CVD 공정은 주로 STI 와 알루미늄 배선간의 갭을 실리콘 산화막 ($SiO_2$)의 절연막으로 채우는 데 주로 사용되고 있다. 이 논문에서는 새로 개발된 HDP CVD 법을 적용하여 300 mm Si 웨이퍼에 $SiO_2$ 절연막을 증착하여 웨이퍼의 중심과 가장자리의 deposition uniformity를 nano-indenter system을 이용하여 연구하였으며, 그 결과 300 mm 웨이퍼에서 균일한 탄성계수 값이 측정되었다. 또한 HDP CVD로 제작된 SiO2 박막의 탄성계수 값이 99 - 107 GPa로 측정되어 기존 PECVD-$SiO_2$ 박막보다 약 10 - 20% 향상된 것을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.109-110
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• 2007

Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.81-87
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• 2010

In this paper, we have fabricated $SiO_2$ oxidation thin films by HDP-CVD(high density plasma-chemical vapor deposition) method for passivation layer or barrier layer of OLED(organic light emitting diode). We have control and estimate the deposition rate and relative index characteristics with process parameters and get optimized conditions. They are gas flow rate($SiH_4:O_2$=30:60[sccm]), 70 [mm] distance from source to substrate and no-bias. The WVTR(water vapor transmission rate) is 2.2 [$g/m^2$_day]. Therefore fabricated thin film can not be applied as passivation layer or barrier layer of OLED.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.39-43
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• 2010

According to recent changes in industry for the semiconductor device, a gap between patterns in wafer is getting narrow. And this narrow gap makes a failure of uniform deposition between center and edge on the wafer. In this paper, for solving this problem, we analyze and manipulate the gas flow inside of the HDP CVD chamber by using CFD(Computational Fluid Dynamics). This simulation includes design manipulations in heights of the chamber and shape of center nozzle in the upper side of the chamber. The result of simulation shows 1.28 uniformity which is lower 3% than original uniformity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.31-38
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• 2002

In order to improve the 0.35 $mutextrm{m}$-via hole etching process the etching characteristic of the gas $C_2F_{6}$ has been analyzed. The samples were triple-layer films(TEOS/SOG/TEOS) on 8-inch wafers and the orthogonal array matrix technique was used for the process. The equipment for etching was the transformer coupled plasma (TCP) source which is a type of high density plasma(HDP). This experiment showed the etching rate for $C_2F_{6}$ was 0.8 $mutextrm{m}$/min-1.1 $mutextrm{m}$/min and the measured uniformity was under $pm$6.9% in the matrix window. The CD skew comparison between pre and post-etching was under 10% which is an outstanding results in the window of profile in anisotropic etching. There was no problem in C2F6 with the flow rate of 20sccm, but when 14sccm of $C_2F_{6}$ was supplied there was a recess problem on the inner wall of SOG film. Consequently the etching characteristic of $C_2F_{6}$ shows a fast etching rate and a very wide process window in HDP TCP.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.151-152
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• 2007

최근들어 Device 크기가 100nm 이하로 줄어듦에 따라 High Density Plasma Chemical Vapor Deposition(HDP-CVD) 기술로는 100nm 이하의 gap에 Aspect ratio가 6:1 이상 되는 STI(Shallow Trench Isolation) 구조를 Void 없이 채우는 것이 불가능해 지고 있다. 이를 극복하기 위하여 여러 방면으로 연구가 수행되어지고 있다. 그 방법 중의 하나인 Dep/Etch/Dep Cycle이 이번 연구에서 사용되었으며, 일반적인 HDP CVD보다 더 낮은 압력에서 증착과 식각이 수행되었다. 그 결과 다른 여러 방법들보다 좋은 막질을 얻을 수 있었으며, Gap fill 성능을 향상 시킬 수 있었다.