• Title/Summary/Keyword: HD video

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Multi-Threaded Parallel H.264/AVC Decoder for Multi-Core Systems (멀티코어 시스템을 위한 멀티스레드 H.264/AVC 병렬 디코더)

  • Kim, Won-Jin;Cho, Keol;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.43-53
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    • 2010
  • Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

Tile-level and Frame-level Parallel Encoding for HEVC (타일 및 프레임 수준의 HEVC 병렬 부호화)

  • Kim, Younhee;Seok, Jinwuk;Jung, Soon-heung;Kim, Huiyong;Choi, Jin Soo
    • Journal of Broadcast Engineering
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    • v.20 no.3
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    • pp.388-397
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    • 2015
  • High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

A Study on 8-VSB/MH Hybrid 3DTV Multiplexer Development based on ATSC2.0 (ATSC2.0 8-VSB/MH 융합형 3DTV 다중화기 개발에 관한 연구)

  • Kim, Sung-Hoon;Kim, Hui Yong;Jung, Kyeong-Hoon
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2016.06a
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    • pp.295-296
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    • 2016
  • 본 논문은 ATSC2.0 기반 8-VSB/MH 융합형 3DTV (A/104 Part 5 Service Compatible 3DTV using Main and Mobile Hybrid Delivery) 방식 다중화기 개발에 대한 내용을 기술한다. ATSC A/104 Part 5 SC-MMH 3DTV 방식은 미국의 지상파 DTV 표준화 논의단체인 ATSC 에서 고정 HD 서비스를 위한 8-VSB 채널과, In-band 모바일 TV 서비스를 위한 ATSC M/H 채널을 이용하여, 주파수 효율을 극대화한 새로운 개념의 3D 콘텐츠 전송기술을 도입한 HD 급 지상파 3DTV 방식으로 2014 년 8 월 융합형 3DTV 서비스 시그널링 방안 및 2015 년 10 월 부가정보(VEI: Video Enhancement Information)를 이용한 화질개선 기술을 ATSC 3DTV Standard 로 채택하였다. 본 논문에서는 이와같은 8-VSB/MH 융합형 3DTV Head-End 핵심장비인 8-VSB/MH 융합형 3DTV 다중화기 구현에 대한 내용을 기술한다.

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System Design of High-Definition Media Transceiver based on Power Line Communication and Its Performance Analysis (전력선 통신 기반 HD급 미디어 전송 시스템 설계 및 성능 분석)

  • Kim, Ji-Hyoung;Kim, Kwan-Woong;Kim, Yong-K.
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.1
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    • pp.192-196
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    • 2010
  • Due to a development of a modem technology as Power Line Communication(PLC) over 200 Mbps, the high-speed multi-media data trasmission could be currently possible. The strength of the PLC has no more additional wiring work. PLC has also possible to high quality data transmission with currently electrical cable. It has a various strong point campare with existing wire and wireless communication technologies. In This paper we develop a high quality media transmitter-receiver based on merging the HomePlug AV, which is 200 Mbps class PLC technology and HDMI Interface technology. The video function was used for the VEDEO TEST GENERATOR in order to a property valuation. Smart Live 6 software were used for the assessment of audio property. As the result of measurement of the HD class images by capturing from the receiver of the PLC, the quality of images couldn't be confirm any deterioration, which has compared with original reflections. In case of audio part as the result of confirmation of the Phase, Magnitude, it has been confirmed that over 90% of nomal transmition and receiving of acoustic signal. It can be possible to have HD class Media service through the PLC.

A design of CAVLC(Context-Adaptive Variable Length Coding) for H.264 (H.264 CAVLC(Context-Adaptive Variable Length Coding)설계)

  • Lee, Yong-Ju;Suh, Ki-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.108-111
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    • 2008
  • In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

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English Digital Signal Processing Circuit in HD Monitor using Synchronization Signal Optimization (동기신호 최적화 기법을 통한 고품위급 모니터의 디지털 신호처리회로 구현)

  • 천성렬;김익환;이호근;하영호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11C
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    • pp.1152-1160
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    • 2003
  • Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

Development of UWB Sinuous Antenna with Dielectric Lens for 3~6 GHz Band Application (유전체 렌즈를 가진 3~6GHz대용 UWB 시뉴어스 안테나 개발)

  • Lee, Dong Real
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.15 no.6
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    • pp.239-244
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    • 2015
  • Recently, Impulse radars using UWB technologies are widely use for measuring distance, or for transmitting uncompressed high resolution videos. However, since the UWB band spans over octave bands, it is not easy to design such a system. Wide band impedance matching is required for antennas and other RF area. In this study, we designed and fabricated sinuous antenna for 3~6 GHz octave band application. We also designed and attached a dielectric lens to improved the directional gain of the antenna. The gain of the antenna was 6~10 dBi. The dielectric lens attached sinuous antenna was used to transmit HD video data. The maximum reach distance was 90 meter with 10mW power.

Head/Rear Lamp Detection for Stop and Wrong Way Vehicle in the Tunnel (터널 내 정차 및 역주행 차량 인식을 위한 전조등과 후미등 검출 알고리즘)

  • Kim, Gyu-Yeong;Do, Jin-Kyu;Park, Jang-Sik;Kim, Hyun-Tae;Yu, Yun-Sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.601-602
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    • 2011
  • In this paper, we propose head/rear lamp detection algorithm for stopped and wrong way vehicle recognition. It is shown that our algorithm detected vehicles based on the experimental analysis about the color information of vehicle's lamps. The simulation results show the detection rate about stopped and wrong way vehicles is achieved over 94% and 96% in the tunnel HD(High Definition) video image.

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Deblocking Filter Based on Edge-Preserving Algorithm And an Efficient VLSI Architecture (경계선 보존 알고리즘 기반의 디블로킹 필터와 효율적인 VLSI 구조)

  • Vinh, Truong Quang;Kim, Ji-Hoon;Kim, Young-Chul
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11C
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    • pp.662-672
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    • 2011
  • This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

A Scheduling System for MPEG-2 Digital Broadcasting (MPEG-2 디지털 방송을 위한 송출 스케줄링 시스템)

  • Hwang, Kyung-Min;Kim, Jong-Moon;Kim, Tae-Hyun;Cho, Tae-Beom;Jung, Hoe-Kyung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.06a
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    • pp.117-120
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    • 2007
  • It has able to be possible that expression and store visual image from analog to digital without picture quality damaged via improvement of video compression technology. And also, It is possible to broadcasting digital image via transmission of digital image on MPEG-2 standardization. for this reason, the broadcasting business owners have converted broadcasting service from analog to digital. But, local SO(System Operator) has a difficult point which secure HD(High Definition) broadcasting program. In this paper, we designed and implemented Scheduling System for MPEG-2 Digital broadcasting which gather HD broadcasting program from major broadcasting business owners(as like MBC, KBS, SBS, etc) and broadcast them.

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