• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.448-461
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• 2011

H.264/AVC significantly outperforms the previous video coding standards with many new coding tools. Among these tools, several intra-block coding tools can particularly improve coding efficiency. For intra prediction, H.264/AVC supports most probable mode in the entropy coding process to reduce syntax elements indicating intra prediction modes and most probable mode selection ratio is very high. Also, in general, natural images and videos have many homogeneous regions whose high correlation with neighbouring blocks. In this paper, we propose intra prediction mode SKIP mode using decoder-side prediction to improve the coding efficiency. The proposed method is determined the optimal prediction mode using only neighbouring block's information and coded on the basis of the conventional prediction/transform coding. And the prediction modes are not send to decoder at all. Skipped intra prediction mode is determined by decoder. Experimental results show that the proposed method achieves coding gains of 1.40% for common intermediate format(CIF), 3.24% for 720p sequences against the H.264/AVC JM 17.0 reference software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Journal of Broadcast Engineering
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• v.15 no.3
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• pp.380-390
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• 2010

The most recent standard video codec, H.264/AVC achieves significant coding efficiency by using a rate-distortion optimization(RDO). The RDO is a measurement for selecting the best mode which minimizes the Lagrangian cost among several modes. As a result, the computational complexity is increased drastically in encoder. In this paper, a method for fast intra prediction mode decision is proposed to reduce the RDO complexity. To speed up Intra$4{\times}4$ and Chroma Intra encoding, the proposed method decides the case that MPM (Most Probable Mode) is the best prediction mode. In this case, the RDO process is skipped, and only MPM is used for encoding the block in Intra$4{\times}4$. And the proposed method is also applied to the chroma Intra prediction mode in a similar way to the Intra$4{\times}4$. The experimental results show that the proposed method achieves an average encoding time saving of about 63% with negligible loss of PSNR (Peak Signal-to-Noise Ratio).

• ETRI Journal
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• v.28 no.4
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• pp.425-434
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• 2006

We propose a fast macroblock mode prediction and decision algorithm based on contextual information for Pslices in the H.264/AVC video standard, in which the mode prediction part is composed of intra and inter modes. There are nine $4{\times}4$ and four $16{\times}16$ modes in the intra mode prediction, and seven block types exist for the best coding gain based on rate-distortion optimization. This scheme gives rise to exhaustive computations (search) in the coding procedure. To overcome this problem, a fast inter mode prediction scheme is applied that uses contextual mode information for P-slices. We verify the performance of the proposed scheme through a comparative analysis of experimental results. The suggested mode search procedure increased more than 57% in speed compared to a full mode search and more than 20% compared to the other methods.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.175-178
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• 2009

H.264/AVC is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. In this paper, we explained Intra Prediction in H.264/AVC, which is able to achieve higher compressing efficiency from correlation removal of adjacent samples in spatial domain, and proposed efficient Intra Predictor architecture design for H.264/AVC decoder. The proposed system reduced computation cycle using processing element and precomputation processing element and also reduced the number of access to external memory using efficient register. We designed the proposed system with Verilog-HDL and verified with suitable test vector. The proposed Intra Predictor achieved about 60% cycle reduction comparing with existing Intra Predictors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1830-1838
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• 2012

The intra prediction and the motion estimation of inter prediction occupy 70 ~ 80% of whole compression time in H.264/AVC. Compression efficiency has been higher, but complexity has increased and coding time has also increased much more. This paper proposes a block size decision method of the intra prediction and mode decision method which minimize the loss of video quality during the encoding and shorten the time spent. This paper, in addition, proposes an algorithm which determines the method of adaptive block mode for motion estimation of inter prediction. We investigated PSNR and the intra prediction and inter prediction of time-consuming calculations in order to measure video quality degradation and complexity through experiments. Consequently, when you use all three methods, these methods showed that average coding time is shortened as about 500 to 600ms in every frame in the case of all experimented videos, keeping video quality nearly similar, compared with existing methods of H.264.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.133-142
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• 2005

In this paper, two digital video scrambling methods are proposed as simple means of the digital content protection techniques. One is inter block scrambling using motion vector, the other is intra block scrambling using intra prediction mode. The proposed inter block scrambling method distorts the original sequences by swapping horizontal and vertical components of motion vector. This method can be applied on most common video coding techniques such as MPEG-1, 2, 4, H.264, etc. The proposed intra block scrambling method distorts the original sequences by modifying intra prediction mode that is property of H.254 video coding technique. Both methods do not cause my bit rate increase after scrambling. Moreover, they have low complexity because they need only simple operation like XOR. Especially, the proposed intra block scrambling does not distort inter blocks directly. But inter blocks are distorted by error propagation effect as much as intra blocks. This paper introduces two new digital video scrambling method and verifies its effectiveness through simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.