• Title/Summary/Keyword: H.264 intra prediction

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A Fast MB Mode Selection Algorithm in the H.264 Standard (H.264에서의 고속 매크로블록 모드 선택 알고리듬)

  • Kim Donghyung;Jeong Jechang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1C
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    • pp.61-72
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    • 2005
  • For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of MB mode selection. Among all modes which can be selected, $8{\times}8$ and intra $4{\times}4$ mode have higher complexity than the others. So we propose the methods for reduction of the $8{\times}8$ and intra $4{\times}4$ mode complexity by using information of other modes with relatively low complexity. Simulation results show that the proposed methods save up to $54.6{\%}$ of total encoding time while keeping the average decrease about 0.012dB in PSNR.

An Efficient Intra Prediction Mode Decision for Spatial Enhancement Layer (공간 향상 계층에서 효율적인 화면 내 예측 모드 선택 방법)

  • Myung, Jin-Su;Park, Sung-Jae;Oh, Seoung-Jun;Sim, Dong-Gyu;Kim, Byung-Gyu
    • Journal of Broadcast Engineering
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    • v.12 no.5
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    • pp.491-502
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    • 2007
  • In this parer, we propose an efficient intra prediction mode decision scheme in Scalable Video Coding(SVC) which is an emerging video coding standard as an extension of H.264/MPEG-4 AVC(Advanced Video Coding). The proposed method in base on the characteristic of macroblock smoothness follows the statistical analysis of intra prediction mode in an enhancement layer and it decides a candidate intra prediction mode. We also propose an early termination scheme for Intra_BL mode decision where the RD cost value of Intra_BL is utilized. Simulation results show that the proposed method reduces 54.67% of the computation complexity of intra prediction coding, while the degradation in video quality is negligible; for low QP values, the average PSNR loss is very negligible, equivalently the bit rate increases by 0.011%. For high QP values, the average PSNR loss is less than 0.01dB, which equals to 0.249% increase in bitrate.

Enhanced Intra predction for the Characteristics of Color Filter Array (컬러 필터 배열 구조를 고려한 화면 내 예측 개선 기법)

  • Lee, Jae-Hoon;Lee, Chul-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.656-659
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    • 2012
  • In general, images captured by the color filter array are compressed after applying demosaicking process. Since this process introduces data redundancy which can reduce coding efficiency, several methods have been proposed to address this problem. While some conventional approachs convert color format to GBR or YUV 4:2:2 format, we propose to use the YCoCg 4:2:2 format to carry out compression. The proposed method shows an average bits reduction of 3.91% and PSNR increase of 0.04dB compared with H.264 YUV 4:2:0 intra-profile prediction method.

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A Simplification Method of Intra Prediction Considering Importance of Subjective Interest Region (주관적 관심영역 중요도를 고려한 화면내 예측 간소화 방법)

  • Lee, Ho-Young;Kwon, Soon-Kak
    • Journal of Korea Multimedia Society
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    • v.12 no.7
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    • pp.922-928
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    • 2009
  • In H.264 as the newest video standard, 9 modes are used in order to predict the signal values of a block composed with several pixels by intra prediction. From these process, H.264 can bring high compression ratio in the encoded signal but the use of total 9 modes can give the inefficiency of the increase of the complexity induced by the amount of operation processing or the number of searching which is applied to compare adjacent pixels. This paper proposes a simplification method of prediction mode for the intra-picture coding by considering subjective interest region. There are certain region being interested within a picture of the video sequence. This region requires better subjective picture quality than the other regions. The proposed method increases the simplification of prediction mode by providing just essential modes of total 9 modes for less interest regions compared with the interest region. It is possible to get the additional 11%$\sim$15% simplification of the prediction mode by the proposed method, compared with the conventional method which simplifies the prediction mode for all of the picture by using the prediction characteristics only.

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Rate Distortion Improved Mode Decision Method for H.264 Intra Coding (H.264 인트라 프레임의 Rate Distortion 성능 향상을 위한 모드 결정 기법)

  • You, Jong-Min;Choi, Chang-Ryuol;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.8C
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    • pp.591-597
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    • 2008
  • In this paper, we present a improved rate distortion optimization (RDO) for H.264 intra coding. By using new mode decision criteria pass for $I4{\times}4$ in company with the original RDO, the proposed method can achieve the better coding efficiency comparing with the original RDO. Our experimental results show that the proposed algorithm can archive about $0.64{\sim}1.6578%$ bit rate decrease at the same PSNR and $0.049{\sim}0.101dB$ PSNR increase at the same bit rate.

An Efficient Mode Decision Method for Fast Intra Encoding in the SVC Enhancement Layer (SVC 향상 계층의 빠른 인트라 부호화를 위한 효율적인 모드 결정 방법)

  • Cho, Mi-Sook;Kang, Jin-Mi;Chung, Ki-Dong
    • Journal of Korea Multimedia Society
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    • v.14 no.7
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    • pp.872-883
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    • 2011
  • SVC is an emerging video coding standard as an extension of H.264/AVC. This standard uses inter prediction, intra prediction and a new inter-layer prediction to improve coding performance of enhancement layers. However, it has high computational complexity. In this paper, we propose an efficient intra prediction mode decision method in the spatial enhancement layer to reduce the computational complexity. The proposed method consists of two phases. In the first phase, Intra_BL mode is selected using the RD cost of Intra_BL in advance. We exploit the fact that the RD cost and prediction mode are similar to those of neighbor macroblocks. In the second phase, we predict the enhancement layer mode using correlation between intra mode of enhancement layer and that of the base layer. Experimental results show that the proposed method could save from 48.15% to 56.32% in encoding time while degradation in video quality is negligible.

East Algorithm for Intra Prediction in H.264 (H.264의 고속 인트라 예측 알고리듬)

  • 조량석;원치선
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.1952-1955
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    • 2003
  • 최근에 표준화된 H.264 의 인트라 예측은 I-프레임을 압축하는데 사용된다. 최대의 코딩효율을 위해서 부호화기는 모든 인트라 예측 모드를 반복적으로 찾는다. 그러나 이것은 H.264 의 부호화기 복잡도를 매우 크게 하는 단점이 있다. 모든 경우의 모드중에 영상에 따라서는 특히 그 발생 가능성이 높거나 낮은 경우의 모드가 발생한다. 본 논문에서는 에지맵을 이용하여 H.264 의 인트라 예측 모드를 선별적으로 선택하는 방법을 제안한다.

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Implementation and verification of H.264 / AVC Intra Predictor for mobile environment (모바일 환경에서의 H.264 / AVC를 위한 인트라 예측기의 구현 및 검증)

  • Yun, Cheol-Hwan;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.93-101
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    • 2007
  • Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

Adaptive Selection of Weighted Quantization Matrix for H.264 Intra Video Coding (H.264 인트라 부호화를 위한 적응적 가중치 양자화 행렬 선택방법)

  • Cho, Jae-Hyun;Cho, Suk-Hee;Jeong, Se-Yoon;Song, Byung-Cheol
    • Journal of Broadcast Engineering
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    • v.15 no.5
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    • pp.672-680
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    • 2010
  • This paper presents an adaptive quantization matrix selection scheme for H.264 video encoding. Conventional H.264 coding standard applies the same quantization matrix to the entire video sequence without considering local characteristics in each frame. In this paper, we propose block adaptive selection of quantization matrix according to edge directivity of each block. Firstly, edge directivity of each block is determined using intra prediction modes of its spatially adjacent blocks. If the block is decided as a directional block, new weighted quantization matrix is applied to the block. Otherwise, conventional quantization matrix is used for quantization of the non-directional block. Since the proposed weighted quantization is designed based on statistical distribution of transform coefficients in accordance with intra prediction modes, we can achieve high coding efficiency. Experimental results show that the proposed scheme can improve coding efficiency by about 2% in terms of BD bit-rate.

A design of Encoder Hardware Chip For H.264 (H.264 Encoder Hardware Chip설계)

  • Kim, Jong-Chul;Suh, Ki-Bum
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.10a
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    • pp.100-103
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    • 2008
  • In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

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