• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2479-2496
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• 2013

Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.

• Journal of KIISE:Information Networking
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• v.35 no.6
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• pp.510-520
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• 2008

These days, the network convergence for utilizing heterogeneous network on mobile device is being very actively studied. However, understanding characteristics of physical network interfaces and video encoder is needed for using the network convergence technologies efficiently. Thus, this paper proposes an optimized method for streaming video data through different network paths depending on data characteristics and channel condition. Accordingly, unlike the traditional methods, this study divides scalable coded videos by layer importance, the importance of stream information, and the importance in consideration of video decoder's robustness and selectively sends the data via multiple channels. And the experimental results show over 1dB increment in PSNR. The result of this study will provide an optimized video transmission technique in the next generation network convergence environment in which mobile devices have multiple network interfaces.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.712-719
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• 2008

Temporal error concealment indicates the algorithm that restores the lost video data using temporal correlation between previous frame and current frame with lost data. It can be categorized into the methods of block-based and pixel-based concealment. The proposed method in this paper is for pixel-based temporal error concealment using affine transform. It outperforms especially when the object or background in lost block has geometric transform which can be modeled using affine transform, that is, rotation, magnification, reduction, etc. Furthermore, in order to maintain good performance even though one or more motion vector represents the motion of different objects, we defines a cost function. According to cost from the cost function, the proposed method adopts affine error concealment adaptively. Simulation results show that the proposed method yields better performance up to 1.9 dB than the method embedded in reference software of H.264/AVC.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of Broadcast Engineering
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• v.11 no.4 s.33
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• pp.386-395
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• 2006

Multi-view video coding technology demands the very high efficient coding technologies, because it has to encode a number of video sequences which are achieved from a number of video cameras. For this purpose, multi-view video coding introduces the inter-view prediction scheme between different views, but it shows a limitation of coding performance enhancement by adopting only new prediction method. Accordingly, we are going to achieve the more coding performance by enhancing dequantizer perfermance. Multi-view video coding is implemented basically based on H.264/AVC and uses the same quantization/de-quantization method as H.264/AVC does. The conventional quantizer and dequantizer is designed with the assumption that input residual signal follows the Laplacian PDF. However, it doesn't follow the fixed PDF type always. This mismatch between assumption and real data causes degradation of coding performance. To solve this problem, we propose the efficient de-quantization method based on quantized coefficients distribution at decoder without extra information. The extensive simulation results show that the proposed algorithm produces maximum $1.5\;dB{\sim}0.6\;dB$ at high bitrate compared with that of conventional method.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.1-13
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• 2011

In this paper, we propose an adaptive in-loop filter to improve the coding efficiency. Recently, there are post-filter hint SEI and block-based adaptive filter control (BAFC) methods based on the Wiener filter which can minimize the mean square error between the input image and the decoded image in video coding standards. However, since the post-filter hint SEI is applied only to the output image, it cannot reduce the prediction errors of the subsequent frames. Because BAFC is also conducted with a deblocking filter, independently, it has a problem of high computational complexity on the encoder and decoder sides. In this paper, we propose the low-complexity adaptive in-loop filter (LCALF) which has lower computational complexity by using H.264/AVC deblocking filter, adaptively, as well as shows better performance than the conventional method. In the experimental results, the computational complexity of the proposed method is reduced about 22% than the conventional method. Furthermore, the coding efficiency of the proposed method is about 1% better than the BAFC.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.582-584
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• 2011

This paper presents a Channel DiVision (CDV) scheme for transform-domain distributed video coding. In the proposed system, we employ the symmetric motion estimation to generate high quality side information for Wyner-Ziv (WZ) frames. Also, the decoder estimates the distortion of the side information, which is used to classify the transmitting channels for WZ frames. Each channel has a different expected noise. Then, the encoder allocates an appropriate number noise. Then, the encoder allocates an appropriate number present rate-distortion performance results and comparisons with existing state-of-the-art algorithms and H.264.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.176-177
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• 2013

최신 비디오 부호화 표준인 HEVC는 종래의 H.264/AVC에 비해 높은 부호화 효율을 달성하는 반면, 연산 복잡도 또한 크게 증가하여, 제한된 자원을 가진 휴대 단말에서 고화질 및 고해상도 영상의 실시간 복원이 어려운 문제점이 있다. 이러한 문제를 해결하기 위해, 본 논문에서는 HEVC 복호화기의 연산 복잡도를 감소시키기 위한 저 복잡도의 움직임 보상 기술을 제안한다. 제안 방법은 참조 픽셀 간의 유사성을 측정하여, 유사성이 높은 예측 단위에 대해 간략한 보간 필터를 적용함으로써 HEVC 복화기의 연산 복잡도를 감소시킨다. 실험 결과를 통해 제안 방법은 HEVC 복호화기의 연산 복잡도를 최대 13.5%를 감소시킬 수 있으며, 그에 따른 화질 열화는 약 0.48 dB로 크지 않는 것을 확인하였다. 뿐만 아니라, 제안 방법은 임계값의 조절을 통해 연산 복잡도 조절 복호화기의 실현 가능성을 확인할 수 있었다.