• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.296-299
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• 2013

디스플레이 기술이 발전함에 따라 다양한 크기의 디스플레이를 탑재한 장치들이 등장하게 되었고, 다양한 디스플레이 크기만큼 다양한 해상도를 사용하고 있다. 때문에 비디오 코덱과 scaler는 보편적으로 함께 사용된다. 그러나 기존의 scaler는 비디오 코덱의 복호화기와 화면 해상도 변환 모듈이 독립적으로 구성되고, 서로 간에 정보를 이용하지 않으므로 시스템의 성능 개선에 한계가 존재하였다. 즉, 비디오 코덱의 복호화기는 비트스트림으로부터 복호한 정보를 바탕으로 영상을 복원하고, 복원영상은 up/down scaler에서 확대/축소를 수행한다. 하지만 비디오 코덱의 비트스트림에 존재하는 정보는 영상의 특성을 반영하기 때문에 up/down scaler에서 비디오 코덱의 복호화기에서 복호된 정보를 이용하면 복잡도의 증가 없이 효율적인 확대/축소를 수행할 수 있다. 이에 본 논문에서는 비디오 코덱 중 차세대 비디오 코덱인 H.264/AVC 복호화기에서 생성된 복원 영상에 대해서 별도로 영상의 특성을 계산하는 모듈 없이 H.264/AVC 복호화기에서 복원된 정보 중 인트라 모드 정보를 바탕으로 영상의 특성에 맞는 up/down scaler를 구현하는 방법을 제안한다. 이 방법은 기존의 scaler들보다 물체의 경계영역을 더 선명하게 확대하는 효과를 보인다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.800-803
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• 2005

모바일 단말 기반 동영상 서비스 기술에 관한 연구는 최근에 이르기까지 활발히 수행되고 있으며, 인터넷 기반에서 상용화가 가능한 기술 분야를 모바일에 응용하는 시도가 계속되고 있다. 모바일 단말 기반 영상서비스와 관련하여 최신형 모바일 단말에서는 관련기술을 하드웨어적으로 구현하거나 독자적 동영상 압축기술을 적용한 소프트웨어적 구현을 통하여 동영상 서비스를 제공하고 있다. 그러나 상당한 비율을 점하고 있는 기존 모바일 단말에서는 이들 하드웨어 칩이 없거나 추가적으로 애드온(add-on) 할 수 있는 표준적인 방법이 정해지지 않아 최신의 동영상 서비스 기술을 제공받을 수 없다. 따라서 시시각각으로 변화하는 모바일 동영상 서비스 환경에 적극적으로 대처하기 위해서는 소프트웨어적 해결방안이 필수적이라는 인식이 대두되고 있다. 본 연구에서는 모바일 단말에서 소프트웨어 디코더를 이용하여 기존 단말에서 뿐만 아니라 향후 최신단말에서도 적극적으로 대처하기 위하여 H.264/AVC 기반 소프트웨어 디코더를 모바일 단말에 적용하는 방안에 대하여 제안한다.

• ETRI Journal
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• v.31 no.5
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.207-210
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• 2009

An efficient algorithm to compress high dynamic range (HDR) videos is proposed in this work. We separate an HDR video sequence into a tone-mapped low dynamic range (LDR) sequence and a ratio sequence. Then, we encode those two sequences using the standard H.264/AVC codec. During the encoding, we allocate a limited amount of bit budget to the LDR sequence and the ratio sequence adaptively to maximize the qualities of both the LDR and HDR sequences. While a conventional LDR decoder uses only the LDR stream, an HDR decoder can reconstruct the HDR video using the LDR stream and the ratio stream. Simulation results demonstrate that the proposed algorithm provides higher performance than the conventional methods.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.205-216
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• 2010

In this paper, a method of MPEG-2 Transport Stream (TS) multiplexing for Ultra HDTV (UHDTV) and its design and implementation as a SW tool is described. In practice, UHD video may be divided into several HD videos and each video is encoded in parallel. Therefore, it is necessary to synchronize and multiplex multiple bitstreams encoding each HD video for transmitting and storing UHD video. In this paper, it is assumed that 4 HD videos partitioning a UHD spatially are encoded as H.264/AVC and two 5.0 channel audios are encoded by AC-3. Therefore, 4 H.264/AVC elementary streams (ESs) and 2 AC-3 ESs is mainly considered in the TS multiplexing of UHD. For the carriage of H.264/AVC and AC-3 over MPEG-2 TS, PES packetization and TS multiplexing are designed and implemented based on the extended specification of the MPEG-2 Systems and ATSC (Digital audio compressed standard), respectively. The implemented UHD TS multiplexing tool emulates real time HW operation in the time unit corresponding to the duration of one TS packet transmission in a given TS rate. In particular, in order to satisfy the timing model, the buffers defined in the TS System Target Decoder (T-STD) are monitored and their statuses are considered in the scheduling of TS multiplexing. For UHD multiplexing, two kinds of multiplexing structures, which are UHD re-multiplexing and UHD program multiplexing, are implemented and their strength and weakness are investigated. The developed UHD TS multiplexing tool is tested and verified in terms of the syntax and semantics conformance and functionalities by using a commercial analyzer and real-time presentation tools.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.103-106
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• 2004

본 논문에서는 PC 기반 지상파 DMB(Terrestrial Digital Multimedia Broadcasting, T-DMB) 수신기를 위한 SW 최적화에 대해 설명한다. 이 수신기는 PC 외부에 지상파 DMB 신호를 안테나로 수신하여 복조하고 채널 복호하는 프론트 엔드(front-end) 수신 모듈을 이용, USB를 통하여 RS(Reed-Solomon) 부호화된 MPEG-2 TS(Transport Stream) 데이터를 읽어 들여 RS 복호, TS 역다중화, 비디오 복호, 오디오 복호 등의 SW 처리 과정을 거쳐 디스플레이 상에 수신 내용을 표시하게 된다. 본 논문에서는 저사양 PC에서도 T-DMB를 수신할 수 있도록 H.264/MPEG-4 AVC(Advanced Video Coding) 복호 과정을 최적화한 결과에 대해 설명한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.112-115
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• 2009

Inter-Prediction is always the main bottleneck in H.264/AVC Baseline Profile. This paper describes an efficient Inter-Prediction hardware architecture design. H.264/AVC decoder supports various block types such as $16{\times}16$, $16{\times}8$, $8{\times}16$, $8{\times}8$, $8{\times}4$, $4{\times}8$, $4{\times}4$ block types. Reference Software(JM) only considers the $4{\times}4$ block type when the reference block is being fetched. This causes duplicated pixels which needs extra fetch cycles. In order to eliminate some of the duplicated pixels, the $8{\times}8$ and $4{\times}4$ block types were considered in the previous design. If the block size is larger than or equal to the $8{\times}8$ block type, it will be separated into several $8{\times}8$ block types and if the block size is smaller than the $8{\times}8$ block type it will be separated into several $4{\times}4$ blocks. For further reduction of the fetch cycles, the various block types are considered in this paper. As a result, the maximum cycle reduction percentage is 18.6% comparing with the previous design.

• The Journal of the Korea Contents Association
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• v.13 no.6
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• pp.20-29
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• 2013

The compression of video data is intended for real-time transmission of band-limited channels. Compressed video bit-streams are very sensitive to transmission error. If we lose packets or receive them with errors during transmission, not only the current frame will be corrupted, but also the error will propagate to succeeding frames due to the spatio-temporal predictive coding structure of sequences. Error detection and concealment is a good approach to reduce the bad influence on the reconstructed visual quality. To increase concealment efficiency, we need to get some more accurate error detection algorithm. In this paper, We hide specific data into the motion vector difference of each macro-block, which is obtained from the procedure of inter prediction mode in H.264/AVC. Then, the location of errors can be detected easily by checking transmitted specific data in decoder. We verified that the proposed algorithm generates good performances in PSNR and subjective visual quality through the computer simulation by H.324M mobile simulation tool.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.729-730
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• 2006

multimedia applications has been targeted for exploiting single instruction multiple data extensions to instruction architectures for the most of the modern microprocessor. In this paper, the newest video coding standard, H.264/AVC baseline profile decoder has been implemented and optimized exploiting INTEL MMX technology to show the overall system speedup by the SIMD style coding