• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.271-278
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• 2006

Rate-constrained coding is one of the many coding-efficiency oriented tools of H.264/AVC, but mode decision process of RDO(Rate distortion optimization) requires high computational complexity. Many fast mode decision algorithms have been proposed to reduce the computational complexity of mode decision. In this paper, we propose two algorithms for reduction of mode decision in H.264/AVC, which are the fast reference frame selection and selective intra prediction mode decision. Fast reference frame selection is efficient for inter predication and selective intra prediction mode decision can effectively reduce excessive calculation load of intra prediction mode decision. The simulation results showed that the proposed methods could reduce the encoding time of the overall sequences by 44.63% on average without any noticeable degradation of the coding efficiency.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.124-130
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• 2013

In this paper, a new motion estimation algorithm with low-computational complexity is proposed to improve the performance of H.264/AVC. The proposed architecture uses the directions of the median motion vector which is computed by the motion vectors of the three neighbor macroblocks in Integer Motion Estimation. By using the directions of the vector, the proposed architecture has a single computational level instead of multi-computational levels in Integer Motion Estimation. The proposed motion estimation is synthesized using the TSMC 0.18um standard cell library. The synthesis result shows that the gate count is about 217.92K at 166MHz and it was improved about 69% compared with previous one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1098-1107
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• 2005

The emerging H.264/AVC video coding standard improves coding performance significantly by adopting many advanced techniques. This is achieved at the expense of great increasing encoder complexity. Specifically the intra prediction using RDO examines all possible combinations of coding modes, which depend on spatial directional correlation with adjacent blocks. For 4${\times}$4 luma blocks, there are 9 modes, and for 16${\times}$16 luma and 8${\times}$8 chroma blocks, there are 4 modes, respectively. Therefore the number of mode combinations for each macroblock is 592. This paper presents a method to reduce the RDO complexity using simple directional masks and neighboring modes. According to the proposed method, we reduce the number of mode combinations to 132 at the most. Experimental results show the proposed method reduces the encoding time up to $70\%$ with negligible loss of PSNR and bitrate increase compared to the H.264/AVC exhaustive search.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.310-318
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• 2008

The H.264/AVC standard achieves higher coding efficiency than previous video coding standards with the rate-distortion optimization (RDO) technique which selects the best coding mode and reference frame for each macroblock. As a result, the complexity of the encoder have been significantly increased. In this paper, a fast intra-mode decision algorithm is proposed to reduce the computational load of intra-mode search, which is based on the inverse tree-structure edge prediction algorithm. First, we obtained the dominant edge for each $4{\times}4$ block from local edge information, then the RDO process is only performed by the mode which corresponds to dominant edge direction. Then, for the $8{\times}8$ (or $16{\times}16$) block stage, the dominant edge is calculated from its four $4{\times}4$ (or $16{\times}16$) blocks' dominant edges without additional calculation and the RDO process is also performed by the mode which is related to dominant edge direction. Experimental results show that proposed scheme can significantly improve the speed of the intra prediction with a negligible loss in the peak signal to noise ratio (PSNR) and a little increase of bits.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.268-270
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• 2014

본 논문은 FME (Fractional Motion Estimation)의 선택적 수행을 통한 HEVC (High Efficiency Video Coding)의 부호화 고속화 방법을 제안한다. HEVC 는 H.264/AVC 에 비해 약 2 배의 압축 효율을 보이지만, 쿼드트리 구조의 재귀적 호출은 복잡도를 크게 증가시켰다. 이러한 이유로 인하여 HEVC 부호화기의 고속 모드 결정 및 고속화 연구가 활발히 진행되고 있다. 본 논문에서는 HEVC 부호화기 중 가장 높은 복잡도를 갖는 화면 간 예측 모드의 부화소 움직임 추정 (FME: Fractional Motion Estimation)의 선택적 수행을 통하여 부호화기를 고속화하는 방법을 제안한다. 제안하는 방법을 HEVC 레퍼런스 소프트웨어인 HM-12.0 에 적용하여 평균 2.0%의 BD-BR 가 증가하였으나, 평균 36.0%의 부호화 시간 감소 효과를 얻을 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10C
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• pp.983-991
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• 2009

While H.264/AVC is in wide use for multimedia applications such as DMB and IPTV service, we have limited usage cases for embedded real-time applications due to its high computational demand. The paper provides judicious guide line for optimization method selection, by presenting the detailed experiments data through the development process of a real time H.264 software encoder on embedded DSP. The experimental analysis includes an intensive profiling analysis, fast algorithm application, optimal memory assignment, and intrinsic-based instruction selection. We have realized a real-time software that encodes CIF resolution videos 15 fps on TMS320DM64x processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.131-134
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• 2008

H.264/AVC 부호화 표준은 움직임 벡터를 부호화하기 위해 인접 블록이 가지는 다수의 움직임 벡터 중에서 확률적으로 해당 움직임 벡터와 가장 유사한 중간값을 예측 움직임 벡터로 사용한다. 이러한 방법은 다수의 움직임 벡터 중에서 어떤 움직임 벡터가 예측값으로 사용되었는지에 대한 추가 정보 없이 비트량을 효과적으로 감소시킬 수 있는 장점이 있으나, 중간값을 이용한 예측 움직임 벡터는 해당 움직임 벡터를 부호화하는데 소요되는 비트량을 항상 최소로 만드는 최적 예측값이 아니라는 단점이 있다. 이러한 문제를 해결하기 위해 다수의 인접 블록이 가지는 움직임 벡터 중에서 특정 움직임 벡터가 예측값으로 사용되었는지 표현하는 정보를 복호화기에 알려주도록 하여 항상 최적의 예측 움직임 벡터를 선택함으로써 부호화 효율을 향상시킬 수 있으나, 이에 대한 추가 정보를 부호화해야 하는 문제점이 발생하게 된다. 본 논문에서는 부호화기가 부호화 효율 측면에서 가장 우수한 움직임 벡터를 예측값으로 선택하고, 이를 복호화기가 스스로 예측함으로써 인접 블록이 가지는 다수의 움직임 벡터 중에서 특정 움직임 벡터가 예측값으로 사용되었는지에 대한 정보없이 움직임 벡터 부호화에 소요되는 비트량을 효과적으로 감소시키는 움직임 벡터 부호화 방법을 제안한다. 제안한 부호화기는 율-왜곡 측면에서 가장 우수한 예측 움직임 벡터를 선택하고, 복호화기는 부호화기가 선택한 예측 움직임 벡터를 정합 기술을 사용하여 스스로 예측한다. 실험 결과는 제안 방법이 QCIF 및 CIF 영상에서 약 2.2%의 전체 비트량을 감소시킬 수 있음을 보여준다.

• Broadcasting and Media Magazine
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• v.15 no.4
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• pp.45-54
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• 2010

최근 ISO/IEC와 ITU는 공동협력팀(Joint Collaborative Team on Video Coding-JCT-VC)을 구성하여 HEVC(High Efficiency Video Coding)라 불리는 새로운 비디오 압축 표준 기술을 개발하고 있다. JCT-VC의 목표 중 하나는 H.264/AVC 압축률의 2배를 향상하는 것으로 최근 HEVC 테스트 모델(HEVC Test Model - HM)을 확정했다. HM의 여러 기술 중에서 확장 블록 구조 (large block structure) 기술은 CTB(Coded Tree Block)와 TU(Transform Unit), PU(Partition Unit)로 구성된다. CTB와 TU는 압축 단위와 변환 기술을 확장한 반복적인 문법구조(recursive syntax structure)이며, PU는 H.264/AVC과 동일한형태를 띈다. 확장 블록 구조는CTB, PU, TU의 여러 조합에 의해 다양한 모드를 지원하여 압축 성능은 높아졌지만 HM 부호화기의 복잡도는 증가한다. 본 논문에서는 HM에 채택된 확장블록구조 및 변환 기술에 대해 설명한 후, TMuC 및 HM의 테스트 영상을 이용하여 다양한 최대 CTB 및 TU 크기의 압축성능 및 선택비율을 분석한다.