• Journal of Broadcast Engineering
• /
• v.13 no.2
• /
• pp.222-235
• /
• 2008

Recently, as growing of high definition media services like HDTV and IPTV, fast moving picture manipulation techniques need to meet what those services require. Especially, a fast reduced-size image extracting method is required in the areas of video indexing and video summary Conventional DC image extracting methods, however, can't be applied to H.264/AVC streams since a spatial domain prediction scheme is adopted in H.264/AVC intra mode. In this paper, we propose a theoretical method for extracting a thumbnail image from an H.264/AVC intra frame in the frequency domain. Furthermore, the proposed scheme can extract the thumbnail very fast since all operations are applied to transform coefficients directly, after a general equation for the thumbnail extraction in nine H.264/AVC intra prediction modes is introduced, an LUT(Look Up Table) for each mode is designed. Through the implementation and performance evaluation, while the subject quality difference between the output of our scheme and a conventional output is negligible, the former can extract the thumbnail faster then the latter by up to 63%.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.1
• /
• pp.113-120
• /
• 2020

The multi-view video is a collection of multiple videos capturing the same scene at different viewpoints. Thus, there is an advantage of providing for user oriented view pointed video. This paper is suggested that the compression performance of layered depth image structure expression has improved by using more improved method. We confirm the data size of layer depth image by encoding H.264 technology and the each performances of reconstructed images. The H.264/AVC technology has easily extended for H.264 technology of video contents. In this paper, we suggested that layered depth structure can be applied for an efficient new image contents. We show that the huge data size of multi-view video image is decreased, and the higher performance of image is provided, and there is an advantage of for stressing error restoring.

• The Journal of the Korea Contents Association
• /
• v.8 no.5
• /
• pp.29-37
• /
• 2008

To transmit video bit stream over low bandwidth such as wireless channel, high compression algorithm like H.264 codec is exploited. In transmitting high compressed video bit-stream over low bandwidth, packet loss causes severe degradation in image quality. In this paper, a new algorithm for recovery of missing or erroneous motion vector is proposed. Considering that the missing or erroneous motion vectors in blocks are closely correlated with those of neighboring blocks. Motion vector of neighboring blocks are clustered according to average linkage algorithm clustering and a representative value for each cluster is determined to obtain the candidate motion vector sets. As a result, simulation results show that the proposed method dramatically improves processing time compared to existing H.264/AVC. Also the proposed method is similar to existing H.264/AVC in terms of visual quality.

• Journal of Internet Computing and Services
• /
• v.17 no.4
• /
• pp.11-17
• /
• 2016

In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3C
• /
• pp.271-278
• /
• 2006

Rate-constrained coding is one of the many coding-efficiency oriented tools of H.264/AVC, but mode decision process of RDO(Rate distortion optimization) requires high computational complexity. Many fast mode decision algorithms have been proposed to reduce the computational complexity of mode decision. In this paper, we propose two algorithms for reduction of mode decision in H.264/AVC, which are the fast reference frame selection and selective intra prediction mode decision. Fast reference frame selection is efficient for inter predication and selective intra prediction mode decision can effectively reduce excessive calculation load of intra prediction mode decision. The simulation results showed that the proposed methods could reduce the encoding time of the overall sequences by 44.63% on average without any noticeable degradation of the coding efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.24-30
• /
• 2010

In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of $176{\times}144$. As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.5
• /
• pp.12-19
• /
• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.28-34
• /
• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.4
• /
• pp.699-706
• /
• 2008

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remoye blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory sire is reduced and the throughput of the deblocking filter processing is increased. The designed deblocking filter further enhances the parallelism by simultaneously executing horizontal and vertical filtering within a macroblock in pipeline method and adopting overlap between macroblocks. The implementation result shows that the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times than that of the conventional deblocking filter. Hence the Proposed architecture of deblocking filter is able to perform real-time deblocking in high-resolution($2048{\times}1024$) video applications.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.4 s.316
• /
• pp.8-16
• /
• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of K264/AVC standard encoder is greatly increased. Specifically, the inter/intra mode decision method using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision. In the proposed method, we reduce the complexity of the $4{\times}4$ mode decision process using $4{\times}4$ simple square filters, and using spatial block correlation method. Additionally, exploiting the best mode of sub_macroblock in $Inter8{\times}8$ mode, we proposed an algorithm to eliminate some intra modes in current macroblock mode decision process. In addition, we employed a method to raise the probability to select SKIP, $Intra16{\times}16$, and $Intra16{\times}16$ modes which usually show low complexity and low bitrate compared with other modes. From the simulation results, the proposed algorithm reduce the encoding time by maximum 83% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.