• Journal of Power Electronics
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• v.11 no.6
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.270-279
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• 2018

This paper elucidates a hysteresis current controller for enhancing the performance of static synchronous compensator (STATCOM) using cascaded H-bridge multilevel inverter. Due to the rising power demand and growing conventional generation costs a new alternative in renewable energy source is gaining popularity and recognition. A five level single phase cascaded multilevel inverter with two separated dc sources, which is energized by photovoltaic - wind hybrid energy source. The voltages across the each dc source is balanced and standardized by the proposed hysteresis current controller. The performance of STATCOM is analyzed by connecting with grid connected system, under the steady state & dynamic state. To reduce the Total Harmonic Distortion (THD) and to improve the output voltage, closed loop hysteresis current control is achieved using PLL and PI controller. The performance of the proposed system is scrutinized through various simulation results using matlab/simulink and hardware results are also verified with simulation results.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.433-434
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• 2013

본 논문에서는 절연타입의 Half-bridge 구조를 이용하여 입력단을 구성하고 출력단에 5레벨의 출력전압을 생성할 수 있는 새로운 구조의 멀티레벨 PWM 인버터를 제안한다. 기존의 Cascaded H-bridge 멀티레벨 인버터는 두 대의 H-Bridge 인버터 모듈을 직렬 결합하여 5레벨의 출력전압을 생성하는 방식이며, 제안하는 방식은 기존 멀티레벨 인버터의 기본 모듈인 H-bridge의 전원을 절연타입의 Half-bridge 구조를 이용하여 구성하고 스위칭 소자 1개와 다이오드 1개를 추가한 구조이다. 동일한 5레벨의 출력전압 생성 시 기존 방식은 2차 측에 8개의 스위칭 소자가 사용되는 반면 제안된 방식은 5개의 스위칭 소자와 1개의 다이오드가 사용되기 때문에 스위칭 손실 및 부피를 줄일 수 있으며 입력단과 출력단 사이의 절연으로 인한 시스템의 안정성을 확보할 수 있다. PSIM 기반의 컴퓨터 시뮬레이션을 통해 제안된 멀티레벨 인버터의 타당성을 검증한다.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.4
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• pp.448-456
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• 2012

This paper presents a multilevel inverter configuration which is designed by insertion of a bidirectional switch between capacitive voltage sources and a conventional H-bridge module. The modified inverter can produce a better sinusoidal waveform by increasing the number of output voltage levels. By serial connection of two modified H-bridge modules, it is possible to produce 9 output voltage levels including zero. There are 24 basic switching patterns with the 9 output voltage levels. Among the patterns, we select the 2 most efficient switching patterns to get a lower switching loss and minimum dv/dt stress. We then analyze characteristics of Total Harmonic Distortion (THD) of the output voltage with variation of input voltage by computer-aided simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.95-101
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• 2017

A simple and practical voltage balance method for a solid-state transformer (SST) is proposed to reduce the voltage difference of cascaded H-bridge converters. The tolerance device components in SST cause the imbalance problem of DC-link voltage in the H-bridge converter. The Max/Min algorithms of voltage balance controller are merged in the controller of an AC/DC rectifier to reduce the voltage difference. The DC-link voltage through each H-bridge converter can be balanced with the proposed control methods. The design and performance of the proposed SST are verified by experimental results using a 30 kW prototype.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.11
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• pp.645-651
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• 2002

In this paper, a multilevel PWM inverter employing a cascaded transformer is presented to reduce the harmonics of output voltage and load currents. The proposed PWM inverter consists of two full-bridge modules and their corresponding transformers. The secondarics of each transformer are series-connected. So continuous output voltage levels can be synthesized from the suitable selection of the turns ratio of trasformer. And it appears an integral ratio to input DC source. Because of the cascaded connection of transformers, output filter inductor is not necessary. The operational principles and analysis are explained, and it is compared with a conventional isolated H-bridge PWM inverter. The validity of proposed multilevel inverter is verified through simulated and experimental waveform and their FFT results.

• Proceedings of the KIEE Conference
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• 2005.10a
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• pp.93-96
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• 2005

This paper describes experimental analysis of UPQC, which is composed of cascaded H-bridges and single-phase multi-winding transformers. The operational characteristic was analyzed through experimental works with a scaled model, and simulations with PSCAD/EMTDC. The UPQC proposed in this paper can be directly connected to the distribution line without series injection transformers. It has flexibility to expand the operation voltage by increasing the number of H-bridge modules. The analysis results can be utilized to design the actual UPQC system applicable for the actual distribution system.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• Journal of Power Electronics
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• v.16 no.2
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• pp.490-497
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• 2016

The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.316-325
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• 2013

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.