• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.243-250
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• 2001

This paper presents the structure of a $\mu$Spring package, its fabrication process and an analysis of its electrical characteristics compared to that of a $\mu$BGA. It was found that both $\mu$BGA and $\mu$Spring packages provide with outstanding high speed signal transmission characteristics due to their lower inductance of package interconnection lines, smaller than half of inductance of TSOP package lines. Even the worst case substrate trace of a Rambus DRAM $\mu$Spring package yields the line inductance of 2.9nH, which provides with 25% margin compared to the Rambus DRAM specification of 4nH. The fabrication cost of $\mu$Spring package is lower than that of $\mu$BGA by 50%, passes 1000 thermal cycles, meets JEDEC Level 1 specification whereas $\mu$BGA does not, and thereby yields high reliability and strong competing power.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1682-1688
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• 2017

In modern society, the number of industrial customers using equipment sensitive particularly to voltage sags is rapidly increasing. As voltage sags can cause loss of information as well as false operation of the control device, it results in the vast economic damage in industrial processes. One way to mitigate voltage sags in the sensitive loads is the installation of distributed generation (DGs) on the periphery of these loads. In addition, renewable energy sources are currently in the spot light as the potential solution for the energy crisis and environmental issues. In particular, wind power generation which is connected to a grid is rising rapidly because it is energy efficient and also economically feasible compared to other renewable energy sources. On the basis of the above information, in this paper, with Wind Turbine Generators (WTGs) installed nearby the sensitive load, the analysis of the mitigating effect comparison by types of WTGs is performed using voltage sag assessment on the IEEE-30 bus test system. That is, the areas of vulnerability according to types of WTGs are expected to be different by how much reactive power is produced or consumed as WTG reactive power capability is related to the types of WTGs. Using the concept of 'Vulnerable area' with the failure rate for buses and lines, the annual number of voltage sags at the sensitive load with the installation of WTGs per type is studied. This research will be anticipated to be useful data when determining the interconnection of wind power generation in the power system with the consideration of voltage sags.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3587-3593
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• 2009

Nowadays, the PV systems have been focused on the interconnection between the power source and the grid. The PV inverter, either single-phase or three-phase, can be considered as the core of the whole system because of an important role in the grid-interconnecting operation. An important issue in the inverter control is the load current regulation. In the literature, the Proportional+Integral (PI) controller, normally used in the current-controlled Voltage Source Inverter (VSI), cannot be a satisfactory controller for an ac system because of the steady-sate error and the poor disturbance rejection, especially in high-frequency range. By comparison with the PI controller, the Proportional+Resonant (PR) controller can introduce an infinite gain at the fundamental ac frequency; hence can achieve the zero steady-state error without requiring the complex transformation and the dq-coupling technique. In this paper, a PR controller is designed and adopted for replacing the PI controller. Based on the theoretical analyses, the PR controller based control strategy is implemented in a 32-bit fixed-point TMS320F2812 DSP and evaluated in a 3kW experimental prototype Photovoltaic (PV) power conditioning system (PCS). Simulation and experimental results are shown to verify the performance of implemented control scheme in PV PCS.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.69-74
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• 2015

With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.17-26
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• 2010

Pb-Sn solder is rapidly being replaced by lead-free solder for board-level interconnection in microelectronic package assemblies due to the environmental protection requirement. There is a general lack of mechanical reliability information available on the lead-free solder. In this study, thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Experiments are conducted for two types of WB-PBGA packages that have Pb-Sn solder and lead-free solder as joint interconnections. Using real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Bending deformations of the assemblies and average strains of the solder balls are investigated and compared for the two type of WB-PBGA package assemblies. Results show that shear strain in #3 solder ball located near the chip shadow boundary is dominant for the failure of the package with Pb-Sn solder, while normal strain in #7 most outer solder ball is dominant for that with lead-free solder. It is also shown that the package with lead-free solder has much larger bending deformation and 10% larger maximum effective strain than the package with Pb-Sn solder at same temperature level.