• Journal of computational fluids engineering
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• v.8 no.1
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• pp.30-37
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• 2003

The post-processor for two-dimensional flow visualization has been developed by using OOP(object-oriented programming) of Visual C++. User-friendly GUI(graphic user interface) has been built on the base of MFC(Microsoft Foundation Class). The number and order of variables can be specified by user because the input style is the free-format. The new variable can be defined and added to the variable list by using the various operators and functions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1991.04a
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• pp.243-250
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• 1991

This paper concerns the development of NC programming system TIG (Turning with Interactive Graphics) with interactive graphics for turning operation. The system cosists of the processor, the post-processor and the system-user interface. Different from previous segment contour based NC graphic programming systems, the frliability and efficiencyof programming is realized by using Boolean operation with block unit based ICONs for the geometry definition. The tool motion can be also displayed on the screen together with the part contour. The system calculate automatically the number of passes based on the user specified cutting conditions.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.171-177
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• 2013

Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required. Therefore, as in general purpose computer systems, digital signal processor should be designed as multicore architecture as well. Using UTDSP benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2 to 16-core digital signal processor architectures with the cores from simple RISC to in-order and out-of-order superscalar processors for the various window sizes, extensively.

• Journal of Ship and Ocean Technology
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• v.4 no.3
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• pp.33-45
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• 2000

A computational system for wave and viscous flow analysis (WAVIS) has been developed. The system includes a pre-processor, flow solvers and a post-processor. The pre-processor is composed of full form presentation, surface mesh and field grid generation. The flow solvers are for potential and viscous flow calculation. The post-processor has graphic utility for result analysis. All the programs are integrated in a GUI-launcher package. To validate the developed CFD programs of WAVIS, the calculated results for modern commercial hull forms are compared with measurements. It is found that the results from WAVIS are in good agreement with the experimental data, illustrating the accuracy of the numerical methods employed for WAVIS.

• The KIPS Transactions:PartA
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• v.10A no.5
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• pp.479-486
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• 2003

As the Internet appliances like digital TV, Internet set-top boxes, and Internet phone, are showing up in the market, the economics of real-time operating system (RTOS), which is an essential for controlling those devices, is expanding faster than ever before. ETRI has developed describes RTOS called Qplus-P, targeting various platforms ranging from PDA to Internet set-top box and home server. This paper describes the implementation of graphic window library for Qplus-P. The Qplus-P graphic window library was implemented using tiny-X graphic server and gtk graphic toolkit, which are open source software. To port this library to various aliances, hangul processing, screen rotation, touch screen, and graphic acceleration functions are added to the tiny-X graphic server of the implementd graphic window library. Currently, Qplus-P graphic window is running on ARM-based appliances such as iPaq PDA, Samsung S3C2400 board, Zaurus PDA, and on Home Server that uses x86 processor. Qplus-P graphic library is provided as a of Qplus-P target builder.

• Journal of the Korean Graphic Arts Communication Society
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• v.29 no.1
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• pp.1-21
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• 2011

Because of high demand of color quality of the prints, proof prints are more important for end-user to predict and correct the final prints directly as an intermediate. Thus, proof prints can be used as a reference to take minimum ${\Delta}E^*ab$between the originals and finals in the field. The advantage of proof prints is to predict and correct color easily through the RIP(Raster Image Processor) without printing plates and plate making steps. While, it is thought that the proof systems are almost equivalent to the press in the past, present proof systems are more simple to take proof prints more easily due to the automation and digitalization. This paper addresses a method to perform an accurate profiling according to proof paper types and find optimal proof papers which meet proofing requirement. Although proof papers are matched with ISO 12647-7, we were trying to reduce ${\Delta}E^*ab$, In addition to the above, through the Gamut Mapping and Iteration, We were trying to find optimal proofing conditions.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.3
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• pp.99-105
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• 2014

A graphic processing unit (GPU) can perform the same calculation on multiple data (SIMD: single instruction multiple data) using hundreds of to thousands of special purpose processors for graphic processing. Thus, high efficiency is expected when GPU is used for the generation and correlation of satellite navigation signals, which perform generation and processing by applying the same calculation procedure to tens of millions of discrete signal samples per second. In this study, the structure of a GPU-based GNSS simulator for the generation and processing of satellite navigation signals was designed, developed, and verified. To verify the developed satellite navigation signal generator, generated signals were applied to the OEM-V3 receiver of Novatel Inc., and the measured values were examined. To verify the satellite navigation signal processor, the performance was examined by collecting and processing actual GNSS intermediate frequency signals. The results of the verification indicated that satellite navigation signals could be generated and processed in real time using two GPUs.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• Journal of the KSME
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• v.22 no.6
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• pp.447-451
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• 1982

NASTRAN은 모든 구조물 특히 대형 구조물의 정적 해석(static analysis)뿐 아니라 동적 해석, 구조물과 주변 유체 유동과의 관계, seismic analysis, acoustic analysis등 광범위하게 사용되어 질 수 있는 전산 프로그램이다. KAIST에서는 NASTRAN을 보다 효과적으로 활용하기 위하여 pre-processor, postprocess의 개발에 노력하고 있으며 특히 NASTRAN 해석의 결과를 가시화 하기 위하여 computer graphics를 위한 전산 프로그램인 MOVIE-BYU를 NASTRAN과 연결 시켜 사용하려 시도하고 있다.

• ETRI Journal
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• v.22 no.4
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.