• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.1-6
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• 2016

Image rotation is one of main pre-processing step in image processing or image pattern recognition. It is implemented with rotation matrix multiplication. However it requires lots of floating point arithmetic operations and trigonometric function calculations, so it takes long execution time. We propose a new high speed image rotation algorithm without two major time-consuming operations. It use just 2 shear translation operations, so it is very fast. In addition, we apply a parallel computing technique with CUDA. CUDA is a massively parallel computing architecture using prevailed GPU recently. As GPU is a dedicated graphic processor, it is exellent for parallel processing of pixels. We compare the proposed algorithm with the conventional rotation one with various size images. Experimental results show that the proposed algorithm is superior to the conventional rotation ones.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.401-407
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• 2000

Modern microprocessors exploit instruction-level parallel processing to increase the performance. Especially VLIW processors supported by the parallelizing compiler are used more and more in specific applications such as high-end DSP and graphic processing. Bus-based VLIW architecture was proposed for these specific applications and it was designed to reduce the overhead of forwarding unit and the instruction width. In this paper, a optimizing scheduling compiler developed for the proposed bus-based VLIW processor is introduced. First, the method to model interconnections between buses and resource usage patterns is described. Then, on the basis of the modeling, machine-dependent optimization techniques such as bus-to-register promotion, copy coalescing and operand substitution were implemented. Optimization techniques for general-purpose VLIW microprocessors such as selective scheduling and enhanced pipelining scheduling(EPS) were also implemented. The experiment result shows about 20% performance gain for multimedia application benchmarks.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.707-711
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• 2010

Most relational database systems provide $B^+$-trees as their main index structures, and use bulk-loading techniques for creating new $B^+$-trees on existing data from scratch. Although bulk loadings are more effective than inserting keys one by one, they are still time-consuming because they have to sort all the keys from large data. To improve the performance of bulk loadings, this paper proposes an efficient parallel bulk loading method for $B^+$-trees based on CUDA, which is a parallel computing architecture developed by NVIDIA to utilize computing powers of graphic processor units for general purpose computing. Experimental results show that the proposed method enhance the performance more than 70 percents compared to existing bulk loading methods.

• Korean Journal of Agricultural Science
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• v.22 no.1
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• pp.11-23
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• 1995

The CAD/CAM system for the manufacturing automation is the newest technology in mechanical engineering area and becomes the important research subject nowadays. Most of all hardwares and softwares for the CAD/CAM system used in the our manufacturing companies such as automobile company are developed by the foreign country and the purchasing price of them is very expensive but their applicability to a certain area is very limited. This study was conducted to develope a CAD/CAM system for the design and the automatic manufacturing of the iron pattern shaped with 3 - dimensional free curved surface, and to test its applicability to the design and the manufacturing of the rotary blade. The results obtained from the study are as follow; 1. The CAD system which can process graphic procedures from the free curved surface shaped data was developed with personal computer. 2. The CAM main program was developed. This main program could produce CL data from CAD data file by checking the tool interference according to the cutting mode. 3. The sub. program which can simulate the tool trace from the CL data was developed. 4. The post processor for the Deckel FP2NC NC milling machine from CL data file was developed and the sub program could transmit NC program through modem to NC milling machine was developed. 5. The developed CAM system seemed to be applicable to any other system. Because the measuring results of the cross sectional thickness of the plastic model from the manufacturing iron pattern by the system showed that this system could properly check the tool interference. 6. In took 75~90 hours to manufacture two iron patterns of rotary blade. For the sake of convenience in applying to the other systems, this system was developed in BASIC and FORTRAN computer language and minimum portion of machine language as possible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1030-1033
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• 2005

Today's most equipments that contain embedded system only support simple menus and background graphics. However, as the embedded system is applied for much more various fields and the user's needs for graphical interface become higher, the support for multimedia and moving pictures became an important criterion to evaluate the performance of a equipment. Because the present embedded system uses software to construct display environment, it is difficult to meet the bandwidth for multimedia contents and moving pictures. Using software for graphic also lowers the performance of the main function by overloading the processor. In this paper, we present an OLED/TFT-LCD controller suitable for embedded systems. The architecture we propose is described in HDL and the performance is evaluated in comparison with the existing embedded systems.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.421-429
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• 2000

In present, ATM integrated switching system has been developed to a mixed modules that complexed switching system including maintenance, operation based on B-ISDN/LAN service and plug-in module, , which runs on workstation computer system. Meanwhile, workstation has HMI operation system feature including file system management, time management, graphic processing, TMN agent function. The workstation has communicated with between ATM switching module and clients. This computer system architecture has much burden messages communication among processes or processor. These messages communication consume system resources which are socket, message queue, IO device files, regular files, and so on. Therefore, in this paper we proposed new performance modeling with this system architecture. We will analyze the system bottleneck and improve system performance. In addition, in the future, the system has many additional features should be migrated to workstation system, we need previously to evaluate system bottleneck and redesign it. In performance model, we use queueing network model and the simulation package is used PDQ and C-program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Spatial Information Research
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• v.12 no.1
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• pp.13-27
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• 2004

The current industrial development and the increase of population in Daecheong Reservoir basin have produced a rapid increase of wastewater discharge. This has resulted in problem of water quality control and management. Although many efforts have been carried out, reservoir water quality has not significantly improved. In this sense, the development of water quality management system is required to improve reservoir water quality. The goal of this study is to design a GIS-based water quality management system for the scientific water quality control and management in the Daecheong Reservoir. For general water quality analysis, WASP5 model was applied to the Daecheong Reservoir. A sensitivity analysis was made to determine significant parameters and an optimization was made to estimate optimal values. The calibration and verification were performed by using observed water quality data for Daecheong Reservoir. A water quality management system for Daecheong Reservoir was made by connecting the WASP5 model to ArcView. It allows a Windows-based Graphic User Interface(GUI) to implement all operation with regard to water quality analysis. The proposed water quality management system has capability for the on-line data process including water quality simulation, and has a post processor far the reasonable visualization for various output. The modeling system in this study will be an efficient NGIS(National Geographic Information System) far planning of reservoir water quality management.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.50-60
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• 2010

For the last half a century, the personal computer and software industries have been prosperous due to the incessant evolution of computer systems. In the 21st century, the embedded system market has greatly increased as the market shifted to the mobile gadget field. While a lot of multimedia gadgets such as mobile phone, navigation system, PMP, etc. are pouring into the market, most industrial control systems still rely on 8-bit micro-controllers and simple application software techniques. Unfortunately, the technological barrier which requires additional investment and higher quality manpower to overcome, and the business risks which come from the uncertainty of the market growth and the competitiveness of the resulting products have prevented the companies in the industry from taking advantage of such fancy technologies. However, high performance, low-power and low-cost hardware and software platforms will enable their high-technology products to be developed and recognized by potential clients in the future. This paper presents such a platform for industrial embedded systems. The platform was designed based on Telechips TCC8300 multimedia processor which embedded a variety of parallel hardware for the implementation of multimedia functions. And open-source Embedded Linux, TinyX and GTK+ are used for implementation of GUI to minimize technology costs. In order to estimate the expected performance and power consumption, the performance improvement and the power consumption due to each of enabled hardware sub-systems including YUV2RGB frame converter are measured. An analytic model was devised to check the feasibility of a new application and trade off its performance and power consumption. The validity of the model has been confirmed by implementing a real target system. The cost can be further mitigated by using the hardware parts which are being used for mass production products mostly in the cell-phone market.