• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.1-7
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• 1996

In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1995.06a
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• pp.165-170
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• 1995

In this paper, it is attempted to apply the adaptive digital signal processing to compensate for a linear distortion of a loudspeaker and implement a real time hardware for that purpose. The real time system is implemented by using the DSP56001, a general purpose signal processor, as a host processor and the DSP56200, a cascadable adaptive FIR filter peripheral chip, as an adaptive digital filter. The system has 1000 taps at a 44.1kHz. After inverse modeling of under_compensation_speaker, the system reduces loudspeaker's linear distortions by pre-processing an input audio signal to loudspeaker. The experiment shows satisfactory results; after adaption with white noise as input signal for 60sec, the flat amplitude and linear phase frequency characteristics is found to lie over a wide frequency range of 100Hz to 20kHz.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.68-69
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• 1998

Discriminating the clutter signal from Doppler signal is the main function of CDP(color Doppler processor). Up to now, a general method of eliminating clutter signal is using IIR high pass filter. There are many filters that were introduced in other paper. In this paper, we propose the new method of filtering clutter signal. To the new method, we adopt an appropriate filter that can eliminate clutter filter most effectively.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.211-214
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• 2007

With the recent development of spatial information technology, the relative importance of satellite image contents has increased to about 62%, the techniques related to satellite images have improved, and their demand is gradually increasing. Accordingly, a standard processing method for the whole process of collection from satellites to distribution of satellite images is required in many countries for efficient distribution of images and improvement of their utilization. This study presents the processor standardization technique for the preprocessing of satellite images including geometric correction, orthorectification, color adjustment, interpolation for DEM (Digital Elevation Model) production, rearrangement, and image data management, which will standardize the subjective, complex process and improve their utilization by making it easy for general users to use them

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.283-290
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• 1999

Recently, the ${\mu}$-processor based-controlled systems instead of conventional relays circuitry are widely used to industrial applications, and also those technology is available to railway signalings which are safety-critical systems. However, the safety and reliability of software for those systems are harder to demonstrate than in traditional relays circuitry because the faults or errors can not be analyzed and predicted to those systems. So, the safety problems are crucial more and more in ${\mu}$-processor based-controlled system. In this paper, the Grafcet language, the graphical and mathematical form, is used to obtain the high-level safety and reliability of software control logic. The general description for Grafcet notation are provided. And some partial of interlocking logic are formally modeled and simulated by Grafcet language and graphical windows.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.671-679
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• 1999

In this paper, humidity measurement is accomplished using humidity sensor, dehumidify is implemented using general-purpose $\mu$-processorPIC16C54 and thermoelectric module for control measured humidity and input target humidity value proportionally Pottier module product is variety kind of size and characteristic, very important drawing factor is selection necessary heat sink, which is maintain proper thermal resistance from variety kind of module also. From electronic dehumidifier is manufacture by using thermoelectric module, no sound, no vibration, low power consumption of partial space efficient dehumidify proves the validity of this system.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.631-632
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• 2006

In this paper, acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of Korean Institute of Industrial Engineers
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• v.24 no.4
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• pp.591-600
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• 1998

The scheduling of parallel computing systems consists of two procedures, the assignment of tasks to each available processor and the ordering of tasks in each processor. The assignment procedure is same with a clustering. The clustering is classified into linear or nonlinear according to the precedence relationship of the tasks in each cluster. The parallel computing system can be modeled with a Directed Acyclic Graph(DAG). By the granularity theory, DAG is categorized into Coarse Grain Type(CDAG) and Fine Grain Type(FDAG). We suggest the linear clustering method for the scheduling of CDAG using the genetic algorithm. The method utilizes a properly that the optimal schedule of a CDAG is one of linear clustering. We present the computational comparisons between the suggested method for CDAG and an existing method for the general DAG including CDAG and FDAG.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.187-190
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• 2003

In this paper, the efficient implementation technique of media processing part in the terrestrial and satellite DMB (Digital Multimedia Broadcasting) receiver is presented. To implement the unified multimedia Processor of DMB receiver, we investigated the characteristic of DMB service and the functionality of each processing part in the DMB receiver. To implement the synchronization between audio and video media, we present the general method to use the reference clock of the stream in the DMB receiver. Also we present the method to handle the bit error of the received bitstream within the wireless net work for robust media processor.