• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.765-770
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• 2003

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1301-1307
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• 2004

Reduced pressure chemical vapor deposition(RPCYD) technology has been investigated for the growth of SiGe epitaxial films with two dimensional in-situ doped boron impurities. The two dimensional $\delta$-doped impurities can supply high mobility carriers into the channel of SiGe heterostructure MOSFETs(HMOS). Process parameters including substrate temperature, flow rate of dopant gas, and structure of epitaxial layers presented significant influence on the shape of two dimensional dopant distribution. Weak bonds of germanium hydrides could promote high incorporation efficiency of boron atoms on film surface. Meanwhile the negligible diffusion coefficient in SiGe prohibits the dispersion of boron atoms: that is, very sharp, well defined two-dimensional doping could be obtained within a few atomic layers. Peak concentration and full-width-at-half-maximum of boron profiles in SiGe could be achieved in the range of 10$^{18}$ -10$^{20}$ cm$^{-3}$ and below 5 nm, respectively. These experimental results suggest that the present method is particularly suitable for HMOS devices requiring a high-precision channel for superior performance in terms of operation speed and noise levels to the present conventional CMOS technology.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.457-458
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• 2014

In this paper, quantum mechanical simulations of the double-gate ultra-thin body (DG-UTB) MOSFETs are performed according to the International Technology Roadmap of Semiconductors (ITRS) specifications planned for 2020, to devise the way for on-current ($I_{on}$) improvement. We have employed non-equilibrium Green's function (NEGF) approach and solved the self-consistent equations based on the parabolic effective mass theory [1]. Our study shows that the [100]/<001> Ge and GaSb channel devices have higher $I_{on}$ than Si channel devices under the body thickness ($T_{bd}$) <5nm condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.