• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 1999.10a
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• pp.253-261
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• 1999

It is essential for port planning, coastal zone management and environmental impact study to analyze the variation of current and water quality due to the development of water area and discharged water from the estuary barrage and basin, etc. Mokpo sea area has downstream from a long river and two large basins, the Yongsan river and Yongam-Kumho basins, discharging much of water through water gates for the purpose of flood and prohibition of salt intrusion to the inland fresh water area. In this study, the numerical calculation were carried out for the analysis of diffusion characteristics due to discharging operation, adopting the results of tidal current simulation. ADI method is applied to the governing equation for the movement of sea water and diffusion and 6-point method to the advection terms of diffusion equation. As the results of this study, it is known that the discharging operation causes increasing and/or decreasing of current velocity and enlarging and/or depressing of pollutant diffusion limits depending on the distance from the discharging gates and the modes of discharging operation. To utilize these result, the linked gate operation and the method increasing exchange of sea water must be considered.

• Journal of Korean Port Research
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• v.13 no.2
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• pp.419-426
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• 1999

It is essential for port planning, coastal zone management and environmental impact study to analyze the variation of current and water quality due to the development of water area and discharged water from estuary barrage and basin etc. Mokpo sea area downstreams from a long river and two large basins, the Yongsan river and Yongam-Kumho basins discharging much of water through water gates for the purpose of flood control and prohibition of salt intrusion to the inland fresh water area. In this study, the numerical calculations were carried out for the analysis of diffusion characteristics due to discharging operation, adapting the results of tidal current simulation ADI methord is applied to the governing equation for the movement of sea water and diffusion and 6-point method to the advection terms of diffusion equation. As the results of this study, it is known that the discharging operation causes increasing and/or decreasing of current velocity and enlarging and/or depressing of pollutant diffusion limits depending on the distance from the discharging gates and the mode of discharging operation. To utilize these result, the linked gate operation and the method increasing exchange of sea water must be considered.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.179-187
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• 2003

Recently efficient implementation of finite field operation has received a lot of attention. Among the GF($2^m$) arithmetic operations, multiplication process is the most basic and a critical operation that determines speed-up hardware. We propose a hardware architecture using Mastrovito method to reduce processing time. Existing Mastrovito multipliers using the special generating trinomial p($\chi$)=$x^m$+$x^n$+1 require $m^2$-1 XOR gates and $m^2$ AND gates. The proposed multiplier needs $m^2$ AND gates and $m^2$＋($n^2$-3n)/2 XOR gates that depend on the intermediate term xn. Time complexity of existing multipliers is $T_A$+( (m-2)/(m-n) +1+ log$_2$(m) ) $T_X$ and that of proposed method is $T_X$＋(1＋ log$_2$(m-1)＋ n/2 ) )$T_X$. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, XOR space complexity is increased to 1.18% but time complexity is reduced 9.036%.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1317-1326
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• 1999

As the integration ratio and operation speed increase, it has become an important problem to estimate the dissipated power during the design procedure as a method to reduce the TTM(time to market). This paper proposed a prediction model to estimate the maximum dissipated power of a CMOS logic gate. This model uses a calculational method. It was formed by including the characteristics of MOSFETs of which a CMOS gate consists, the operational characteristics of the gate, and the characteristics of the input signals. As the modeling process, a maximum power estimation model for CMOS inverter was formed first, and then a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. For experiment, several CMOS gates were designed in layout level by $0.6{\mu}m$ layout design rule. The result by comparing the calculated results with those from HSPICE simulations for the gates showed that the gate conversion model has within 5% of the relative error rate to the SPICE and the maximum power estimation model has within 10% of the relative error rate. Thus, the proposed models have sufficient accuracies. Also in calculation time, the proposed models was more than 30 times faster than SPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.5
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• pp.323-331
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• 2019

In this study, a computational model approach for the modeling of hydrodynamic pressures acting on radial gates during strong earthquakes is proposed. The use of the dynamic layering method with the Arbitrary Lagrangian Eulerian (ALE) algorithm and the SIMPLE method for simulating free reservoir surface flow in addition to moving boundary interfaces between the fluid domain and a structure due to earthquake excitation are suggested. The verification and validation of the proposed approach are realized by comparisons performed using the renowned formulation derived by the experimental results for vertical and inclined dam surfaces subjected to earthquake excitation. A parameter study for the truncated lengths of the two-dimensional fluid domain demonstrates that twice the water level leads to efficient and converged computational results. Finally, numerical simulations for large radial gates with different curvatures subjected to two strong earthquakes are successfully performed using the suggested computational model.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.2
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• pp.64-72
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• 2001

Weld line is one of serious troubles which are observed in a plastic part manufactured by a injection molding process. This is caused by many process factors, which are molding pressure, temperature, velocity, location of a injection gate, mold geometry and material properties. investigation on the effects of these process factors to the appearance of a weld line was carried out using a finite element method. Filling and packing analyses were carried out by modifying both the configuration of the injection gates and cavity thickness. Proper locations of the injection gates could be determined by considering molding pressure, temperature, velocity and frozen layer, and whereby the weld line was controled. In order to make a weak appearance of the weld line, flow velocity and flow front in a cavity were also investigated by modifying a cavity thickness. As a result, flow front was extended around the corner in the cavity by changing the flow velocity and hence the appearance of the weld line was much weakened.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.333-336
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• 1999

In this paper, a new high speed parallel input and parallel output GF(2$^{m}$ ) multiplier based on standard basis is proposed. The concept of the multiplication in standard basis coordinates gives an easier VLSI implementation than that of the dual basis. This proposed algorithm and method of implementation of the GF(2$^{m}$ ) multiplication are represented by two kinds of basic cells (which are the generalized and fixed basic cell), and the minimum critical path with pipelined operation. In the case of the generalized basic cell, the proposed multiplier is composed of $m^2$ basic cells where each cell has 2 two input AND gates, 2 two input XOR gates, and 2 one bit latches Specifically, we show that the proposed multiplier has smaller complexity than those proposed in 〔5〕.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.5
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• pp.188-192
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• 1984

A method of frequency multipling of square waveforms is described and an integrable frequency multiplier which is fully compatible with IC technology, and made use of only bipolar transistors and resistors is proposed. The circuit is composed of only integrable time delay circuits and exclusive OR gates. Hence the circuit shows some useful characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.88-99
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• 1992

This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.