• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1117-1122
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• 1999

Amorphous Si and Co/Ti bilayers were sequentially evaporated onto 5- 10nm thick $\textrm{CoSi}_{2}$ and rapidly thermal-annealed(RTA) to form Co-polycide electrodes. Then, MOS capacitors were fabricated by doping poly-Si using SADS method. The C-V and leakage-current characteristics of the capacitors depending upon the RTA conditions were measured to study the effects of thermal stability of $\textrm{CoSi}_{2}$ and dopant redistribution on electrical properties of Co -polycide gates. Capacitors RTAed at $700^{\circ}C$ for 60-80 sec., showed excellent C-V and leakage-current characteristics due to degenate doping of poly-Si layers. But for longer time or at higher temperature, their electrical properties were degraeded due to $\textrm{CoSi}_{2}$ decomposition and subsequent Co diffusion. When making Co-polycide gate electrodes by SADS, not only degenerate doping of poly-Si layer. but also suppression of have been shown to be very critical.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.4
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• pp.260-267
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• 2017

Quantum-inspired Genetic Algorithm (QGA) is a probabilistic search optimization method combined quantum computation and genetic algorithm. In QGA, the chromosomes are encoded by qubits and are updated by quantum rotation gates, which can achieve a genetic search. Asset-based weapon target assignment (WTA) problem can be described as an optimization problem in which the defenders assign the weapons to hostile targets in order to maximize the value of a group of surviving assets threatened by the targets. It has already been proven that the WTA problem is NP-complete. In this study, we propose a QGA and a hybrid-QGA to solve an asset-based WTA problem. In the proposed QGA, a set of probabilistic superposition of qubits are coded and collapsed into a target number. Q-gate updating strategy is also used for search guidance. The hybrid-QGA is generated by incorporating both the random search capability of QGA and the evolution capability of genetic algorithm (GA). To observe the performance of each algorithm, we construct three synthetic WTA problems and check how each algorithm works on them. Simulation results show that all of the algorithm have good quality of solutions. Since the difference among mean resulting value is within 2%, we run the nonparametric pairwise Wilcoxon rank sum test for testing the equality of the means among the results. The Wilcoxon test reveals that GA has better quality than the others. In contrast, the simulation results indicate that hybrid-QGA and QGA is much faster than GA for the production of the same number of generations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Journal of Korean Society of Transportation
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• v.23 no.1
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• pp.33-44
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• 2005

Railroad crossing crashes are fewer than road crashes, but with regard to crash severity, they can be serious injury crashes. There should be, therefore, enormous efforts to increase the safety of railroad crossings. The objective of this paper is to identify and understand factors associated with railroad crossing crashes. Statistical models are used to examine the relationships between crossing accidents and geometric elements of crossings. The results show the Poisson model is the most appropriate method for the crossing accidents, because overdispersion was not observed. This study identifies seven significant factors associated with railroad crossing crashes through the main and variant models. With regard to explanatory factors on crossing safety, the total traffic volume, daily train volume, presence of commercial area around crossings, distance of train detector from crossings, time duration between the activation of warning signals and gates, crossing types, and speed hump were found to affect the safety of railroad crossings.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.589-596
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• 2021

In this study, the optimum gating system was designed, and the two zinc alloy worm gears were manufactured in single process by applying a symmetrical gating system with 2 runners. The SRG ratio is set to 1 : 0.9 : 0.6, and the cross-sectional shapes such as sprue, runner and gate are designed. In order to determine whether the design of the gating system is appropriate, casting analysis was carried out. It takes 4.380 s to charge the casting 100%, 0.55 to 0.6 m/s at the gates and solidification begins after the casting is fully charged. The amount of air entrapment is 2% in the left gear and 6% in the right gear. Hot spots occurred in the center hole of the gear, and pores were found to occur around the upper part of the hole. Therefore, the design of the casting method is suitable for worm gears. CT analysis showed that all parts of worm gear were distributed with fine pores and some coarse pores were distributed around the central hole of worm gear. The yield strength and tensile strength were 220 MPa, 285 MPa, and the elongation rate was 8%. Vickers hardness is 82 HV.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.71-83
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• 2020

In this paper, we propose a system that can detect the shape of a hand at high speed using an FPGA. The hand-shape detection system is designed using Verilog HDL, a hardware language that can process in parallel instead of sequentially running C++ because real-time processing is important. There are several methods for hand gesture recognition, but the image processing method is used. Since the human eye is sensitive to brightness, the YCbCr color model was selected among various color expression methods to obtain a result that is less affected by lighting. For the CbCr elements, only the components corresponding to the skin color are filtered out from the input image by utilizing the restriction conditions. In order to increase the speed of object recognition, a median filter that removes noise present in the input image is used, and this filter is designed to allow comparison of values and extraction of intermediate values at the same time to reduce the amount of computation. For parallel processing, it is designed to locate the centerline of the hand during scanning and sorting the stored data. The line with the highest count is selected as the center line of the hand, and the size of the hand is determined based on the count, and the hand and arm parts are separated. The designed hardware circuit satisfied the target operating frequency and the number of gates.

• Journal of architectural history
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• v.31 no.4
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• pp.17-28
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• 2022

This study aims to investigate and reveal the spatial structure of Boryeonghyeon by examining the geographical status of its Eupchi (Local administrative center:邑治) through an analysis of the location, tracing locations of governemnt offices including Dongheon(東軒) and Kaeksa(客舍) in the walled town, and checking the lot numbers of Sajikdan(社稷壇), Yeodan(厲壇), and Cheongyeonyeok(靑淵驛) outside it. Buildings of Boryeonghyeon in the walled town in the Joseon Dynasty were almost lost and now, part of the city wall and Haesanru(海山樓) just remains as relic. The walled town consisted of several buildings of government offices as well as Dongheon and Kaeksa which are government organs. Altar and shrine(壇廟) facilities including Shrine of Confucius(文廟), Altar of Land and Grain, and Preceptor's Shrine were placed outside the walled town and Cheongyeonyeok were operated as the facilities for transmission of royal orders. Therefore, the government office facilities in the walled town, altar and shrine facilities outside the fortress, and the location of the post station were required to trace and check each of them. For the checking method, the lot numbers could be checked by checking the original cadastral maps and the then land categories and owners, analyzing the records and circumstances of the relevant township annals(邑誌), and examining analyses on the locations by using a numerical map of one to 5 thousands. The study estimated the locations of government facilities including Dongheon and Kaesa placed in the walled town and was grasped to be the east and west gates with the south gate which remains now in the fortress. And the lot numbers of Sajikdan, Yeodan, Cheongyeonyeok.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.180-186
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• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.