• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.

• The Journal of the Korea Contents Association
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• v.17 no.1
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• pp.50-57
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• 2017

This study investigated the causes and problems of train operation impediments through the statistics analysis of 8 years'internal data of Daejeon Metropolitan Express Transit. By evaluating the risks regarding the system, equipment, and parts of high risk group, this study measured the Risk Index Severity, and applied the $5{\times}5$ Risk Assessment Matrix which is a method of risk management to calculate the scale of risk to analyze the safety level and allowance range. As a result, the car sector, the most serious risk, followed by machinery and equipment sector showed that the inherent risk. In particular, the door broken and the door rail signaling and control devices due to defects of the vehicle is high, but also the severity, and frequency are showing very frequent additional potential accidents. PSD also had defects in the machinery sector appeared to be the most dangerous of the PSD poor safety gates, it was found that the glass also involve the risk of mishandling and breakage of the PSD. This study intended to contribute to the transportation benefits through the safety and stable operation of Metropolitan Express Transit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.594-600
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• 2017

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

• Transactions on Electrical and Electronic Materials
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• v.6 no.4
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• pp.154-158
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• 2005

Organic molecules have many properties that make them attractive for electronic applications. We have been examining the progress of memory cell by using molecular-scale switch to give an example of the application using both nano scale components and Si-technology. In this study, molecular electronic devices were fabricated with amino style derivatives as redox-active component. This molecule is amphiphilic to allow monolayer formation by the Langmuir-Blodgett (LB) method and then this LB monolayer is inserted between two metal electrodes. According to the current-voltage (I-V) characteristics, it was found that the devices show remarkable hysteresis behavior and can be used as memory devices at ambient conditions, when aluminum oxide layer was existed on bottom electrode. The diode-like characteristics were measured only, when Pt layer was existed as bottom electrode. It was also found that this metal layer interacts with organic molecules and acts as a protecting layer, when thin Ti layer was inserted between the organic molecular layer and Al top electrode. These electrical properties of the devices may be applicable to active components for the memory and/or logic gates in the future.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of Navigation and Port Research
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• v.38 no.6
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• pp.645-653
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• 2014

A Bridge Navigational Watch Alarm System (hereafter 'BNWAS') is to monitor and detect if an officer of watch(hereafter 'OOW') keeps a sharp lookout on the bridge. The careless lookout of an OOW could lead to marine accidents. For this reason on June 5th, 2009, IMO decided that a ship is equipped with a BNWAS. However, an existing BNWAS gives the OOW a lot of inconvenience and stress in its operation. It requires that the OOW should press reset buttons to confirm their alert watch on the bridge at every three to twelve minute. Many OOWs have complained that at some circumstances they cannot focus on their bridge activities including watch-keeping due to a lots of resetting inputs of BNWAS. Accordingly, IMO has allowed the use of a motion sensor as a resetting device. The motion sensor detects the movements of human body on the bridge and subsequently sends reset signals directly to BNWAS automatically. As a result, OOWs can work uninterrupted. However, some of classification societies and flag authorities have a slightly different stance on the use of motion sensor as a resetting method for BNWAS. The reason is that the motion sensor may trigger false reset signals caused by the motion of objects on the bridge, especially a slight movement such as toss and turn of human body which can extend the period of careless watch. As a basic study to minimize the false reset signals, this paper proposes a simple configuration of BNWAS, which consists of only three motion sensors associated with 'AND' and 'OR' logic gates. Additionally, several considerations are also proposed for the implementation of motion sensors. This study found that the proposed configuration which consists of three motion sensors is better than an existing one by reducing false reset signals caused by a slight movement of human body in one's sleep. The proposed configuration in this paper filters false reset signals and is simple to be implemented on existing vessels. In addition, it can be easily installed just by a basic electrical knowledge.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.6
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• pp.648-653
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• 2012

Cavity pressure, an important factor in injection molding process, should be minimized to enhance injection molding quality. In this study, we decided the locations of valve gates to minimize the maximum cavity pressure. To solve this problem, we integrated MAPS-3D (Mold Analysis and Plastic Solution-3Dimension), a commercial injection molding analysis CAE tool, using the file parsing method of PIAnO (Process Integration, Automation and Optimization) as a commercial process integration and design optimization tool. In order to reduce the computational time for obtaining the optimal design solution, we performed an approximate optimization using a meta-model that replaced expensive computer simulations. To generate the meta-model, computer simulations were performed at the design points selected using the optimal Latin hypercube design as an experimental design. Then, we used micro genetic algorithm equipped in PIAnO to obtain the optimal design solution. Using the proposed design approach, the maximum cavity pressure was reduced by 17.3% compared to the initial one, which clearly showed the validity of the proposed design approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.