• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Journal of the Korean Institute of Oriental Medical Informatics
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• v.16 no.2
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• pp.89-161
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• 2010

"Byun Jeung Rok(辨證錄)" is composed of 14 volumes. In relation to the contents, it is organized into 126 gates(門) and 700 remaining syndromes(餘證) where internal medicine, external medicine, pediatrics, gynecology(內科 外科 小兒 婦人), etc. are divided into sub-sections of cold damage, cold stroke, wind stroke(傷寒 中寒 中風), etc. For every syndrome, the symptom, cause of disease, method of treatment, prescription, construction of prescription, instruction of medicine and prognosis.(症狀 病因 治法 處方 處方構成 服用法 預後) were explained thoroughly. This study, as an inquiry of the second volume, deals with wind stroke(中風), impediment disease(痹證), heart pain(心痛), side pain(脇痛), headache(頭痛), abdominal pain(腹痛), lumbago(腰痛) It was written very logically so it is easy to understand. The analysis of the symptoms are brief and appropriate. Also, in the usage of the medicine, the sovereign, minister, assistant and courier(君臣佐使) method was used as the basis for the prescriptions. Therefore, it is considered to have significant clinical value for future generations and is thus being applied by them.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.14 no.3
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• pp.267-276
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• 2001

On the basis of structural analysis of the radial gate(that is, Tainter gate), this paper focuses on the optimization of the moment distribution according to the location of the arm of the radial gate. In spite of its importance from economical view point, we could hardly find the study on the optimum design of radial gate. Accordingly, the present study identifies the optimum section modulus for a radial arm along with the optimum position for 2 of 3 radial arms with a convex cylindrical skin plate relative to a given radius of the skin plate curvature, pivot point, water depth, ice pressure, etc. These optimum measurements are then compared with previously constructed radial gates. The results indicate that the optimum section modulus vague for a radial arm was appreciably smaller than the previously constructed examples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.1008-1014
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• 2002

This paper is concerned about multiplierless interpolation FIR filters. In this paper, we propose a filter that performs T tap 1:N interpolation FIR filter operation with B-bit inputs without using multipliers. This is done by applying a method which converts a 2s complement multi-bits input to multiple single-bit inputs and a lookup table minimization method which reduces the size of lookup tables by use of the symmetry of filter coefficients and the symmetry of each lookup table. Two FIR filters are implemented using the methods proposed in this paper. Each of the two filters respectively follows the two design parameters in the specification of IMT-2000. Those two FIR filters have an advantage that the number of required gates is reduced up to 70% comparing to that of a conventional transversal FIR filter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.1
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• pp.7-12
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• 2003

The purpose of testability analysis is to estimate the difficulty of testing a stuck-at fault in logic circuits. A good testability measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Conventional testability measurements, such as COP and SCOAP, can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy is due to the ignorance of signal correlations for making the testability analysis linear to a circuit size. This paper proposes an efficient method for computing testability analysis, which takes into account signal correlation to obtain more accurate testability. The proposed method includes the algorithm for identifying all reconvergent fanouts in a given n circuit and the gates reachable from them, by which information related to signal correlation is gathered.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.31-40
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• 2022

This paper proposes an augmented QSBC(Quantum Short-Block Code) that preserves the function of the existing QSBC and adds a single bit-flip error correction function due to Pauli X and Y errors. The augmented QSBC provides the diagnosis and automatic correction of a single Pauli X error by inserting additional auxiliary qubits and Toffoli gates as many as the number of information words into the existing QSBC. In this paper, the general expansion method of the augmented QSBC using seed vector and the realization method of the Toffoli gate of the single bit-flip error automatic correction function reflecting the scalability are also presented. The augmented QSBC proposed in this paper has a trade-off with a coding rate of at least 1/3 and at most 1/2 due to the insertion of auxiliary qubits.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.495-508
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• 2023

This paper proposes a method to find out the type and location information of Pauli X, Y, Z errors generated in quantum channels using only the quantum information processing part of the multiple-rate quantum turbo short-block code without external help from the classical information processing part. In order to obtain the location information of the Pauli X,Y error, n-auxiliary qubits and n-CNOT gates were inserted into the C[n,k,2] QSBC-QURC encoder. As a result, the maximum coding rate is limited to about 1/2 as the trade-off characteristics. The location information of the Pauli Z error for C[n,k,2] QSBC-QURC was obtained through the Clifford-based stabilizer measurement. The proposed method inherits all other characteristics of C[n,k,2] QSBC-QURC except for the coding rate.