• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.196-197
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• 2006

In this paper, two types of vertical SIT(Static Induction Transistor) structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. First, a trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. Second, a trench gate-source region power SIT device is proposed to obtain more higher forward blocking voltage and forward blocking characteristics at the same size. The two proposed devices have superior electrical characteristics when compared to conventional device. In the proposed trench gate oxide power SIT, the forward blocking voltage is considerably improved by using the vertical trench oxide and the forward blocking voltage is 1.5 times better than that of the conventional vertical power SIT. In the proposed trench gate-source oxide power SIT, it has considerable improvement in forward blocking characteristics which shows 1500V forward blocking voltage at -10V of the gate voltage. Consequently, the proposed trench oxide power SIT has the superior stability and electrical characteristics than the conventional power SIT.

• The Journal of Asian Finance, Economics and Business
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• 제8권5호
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• pp.769-775
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• 2021

The objective of this research was to analyze the factors influencing the farm-gate shrimp prices in Thailand using monthly time series from January 2001 to December 2019. The econometric methodology was employed to satisfy the purpose, consisting of the cointegration test for revealing the long-run relationship and equilibrium elasticity between the variables as well as the error correction model for detecting speed adjustment to shock responses. The empirical results revealed that (1) the export shrimp prices, shrimp production in the country, and shrimp export volume indicated a long-run relationship running to the farm-gate shrimp prices in Thailand with the size of equilibrium elasticity equal to 1.083%, -0.256%, and 0.123, respectively, and (2) the farm-gate shrimp prices in Thailand would adjust to the equilibrium line with a speed equal to 20.147% if there was any kind of incident or shock which caused the relationship to deviate from the equilibrium point. There was no relationship in terms of global shrimp prices and the exchange rate for farm-gate shrimp prices in Thailand. The recommendations should emphasize the varieties of shrimp products for export to other countries beyond the main trading markets nowadays to reduce risks and fluctuations in the export prices of shrimp products.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.1-8
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• 2000

본 논문에서는 인터커넥트 라인을 구동하는 CMOS소자의 게이트 폭의 변화에 따라 소자 및 인터커넥트라인에 의한 RC 지연시간이 어떤 특성을 보이는지에 대하여 분석하였다. 인터커넥트 라인의 캐패시턴스 성분만이 주로 나타나는 구조에서는 MOSFET의 크기가 커질수록 전체 지연시간이 감소하는 특성을 보였다. 반면에 인터커넥트 라인의 저항 및 캐패시턴스 성분이 대등하게 지연시간에 영향을 미치는 구조에서는 전체회로의 지연시간이 최소가 되는 MOSFET 크기가 존재함을 수식적으로 제안하고 실험치와 비교하여 잘맞음을 증명하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1168-1171
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• 2007

Integrating systems on TFT-LCD panels is more and more popular for the mobile display application. However, it may not be necessary to use LTPS TFT devices. A-Si TFTs are used to integrate systems on TFT-LCD panels, especially scan (gate) drivers. To further reduce the chip size of driver IC, the triplegate pixel structure is developed. Therefore, the number of the source lines is reduced to 1/3 times.

• 한국농공학회지
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• 제34권2호
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• pp.40-48
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• 1992

A model using a linear programming technique was developed to operate gates for the optimum management of small of medium size agricultural reservoirs. To predict the inflow into the reservoirs the WASHMO model, which was a single event hydrology model, was modified and used. To test the applicability, the developed model was applied to two reservoirs located in Kyungpook province. The results showed that the model could be used for the optimum gate operation of the agricultural reservoirs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.199-202
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• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 1999년도 춘계학술대회논문집
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• pp.169-172
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• 1999

Thixoforming process has been accepted as a new method for fabricating near net shaped products with lighweight aluminum alloys. The thixoforming process consists of reheating process of billet, billet handing filling into the die cavity and solidification of thixoformed part,. in this paper the thixoforming experiments are performed with two different die temperature ({{{{ TAU _d}}}}=20$0^{\circ}C$ 30$0^{\circ}C$) and orifice gate type. The microstructures of SSM(357, A490 and ALTHIX 86S) fabricated in thixoforming process are evaluated in therms of globularization and grain size. effect of alloying elements onthe surface and internal defects is investigated. Finally the methods to obtain the thixoformed products with good mechanical propertis are proposed by solution for avoiding the surface and internal defects.