• Research in Plant Disease
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• v.12 no.2
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• pp.75-80
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• 2006

Crown gall on rose was observed in greenhouse during year 2003-2005. The disease incidence was up to 28.3% and the disease was the severer in hydrophonics culture than that in soil. The typical gall symptom occurred mainly on the root and crown resulting in poor foliage, stunting, and fewer blossoms. Sixty-three rose cultivars were inoculated with Agrobacterium. tumefaciens isolated from rose crown gall, to evaluate rose cultivar-specific resistance. The size of galls from inoculated rose stems was measured in a greenhouse test. Tumors formed in almost varieties of rose inoculated. Based on the frequency of tumor occurrence and weight of galls formed on the stem of rose, it was shown that 'Little Marble', 'Golden Gate' and 'Rosa Rox-ette' were extremely susceptible to crown gall. Some varieties such as 'Little Silver' appeared to be resistant to the crown gall.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.834-841
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• 2018

A power amplifier for subgigahertz short-range wireless communication using $0.18-{\mu}m$ CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of $2.14mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.401-404
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• 2016

This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.246-250
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• 2021

TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (10¹⁷ cm^-3·eV^-1) were used as top gate TFTs channel layer, leading to a high mobility (55 cm²/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.153-153
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• 2021

Storm Storm event is one of major issues in South Korea due to devastating damage at its landfall. A series of statistical study on the historical typhoon records consistently insist that the typhoon translation speed (TS) is on slowdown trend annually, and thus provides an urgent topic in assessing the extreme storm surge under future climate change. Even though TS has been regarded as a principal contributor in storm surge dynamics, only a few studies have considered its impact on the storm surge. The landfall angle (LA), another key physical factor of storm surge also needs to be further investigated along with TS. This study aims to elucidate the interaction mechanism among TS, LA, coastal geometry, and storm surge synthetically by performing a series of simulations on the idealized geometries using Delft3D FM. In the simulation, various typhoons are set up according to different combinations of TS and LA, while their trajectories are assumed to be straight with the constant wind speed and the central pressure. Then, typhoons are subjected to make landfall over a set of idealized geometries that have different depth profiles and layouts (i.e., open coasts or bays). The simulation results show that: (i) For the open coasts, the maximum surge height (MSH) increases with increasing TS. (ii) For the constant bed level, a typhoon normal to the coastline resulted in peak MSH due to the lowest effect of the coastal wave. (iii) For the continental shelf with different widths, the slow-moving typhoon will generate the peak MSH around a small LA as the shelf width becomes narrow. (iv) For the bay, MSH enlarges with the ratio of L/E (the length of main-bay axis /gate size) dropping, while the greatest MSH is at L/E=1. These findings suggest that a fast-moving typhoon perpendicular to the coastline over a broad continental shelf will likely generate the extreme storm surge hazard in the future, as well as the slow-moving typhoon will make an acute landfall over a narrow continental shelf.