• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2006.05a
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• pp.363-366
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• 2006

The delivery system such as sprue, runner and gate is a waste of resin in injection molding operation. In this study the reduction of runner size has been investigated using injection molding CAE softwares, Moldflow and Moldex, and commercial CFD Softwares, Fluent and Polyflow. To verify the computational results experiment was performed. There were three considerations in deciding optimal runner size in this study: minimum pressure at the gate that makes resin fully filled in the cavity, minimum runner size that compensates shrinkage of resin in the cavity, and frozen layer thickness formed in the runner during injection. Through the computer simulations the optimal runner size that satisfies those three considerations has been decided. Although the computational results among the softwares were slightly different, it was enough to predict, the optimal runner size. The previous runner diameter was 8 mm and predicted optimal size was 5 mm. This was verified by injection molding experiment. Thus, the way of CAE application in deciding optimal runner size adapted in this study would be appropriated.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.165.2-165.2
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• 2011

Flow with suction to water turbine must be in stable state at small hydraulic power plant. But because of water level fluctuation and water gate effect according to irregular supply of cooling water, it would happen to produce bubble and vortex and finally lead to problems in power-plant system. With utilizing the concept design of double size gate, surface water overflowed the overhead of gate for stable flow at suction. We developed the overflow condition and analyzed the design factor with existed one such as water level(overflow amount) and overhead of water gate(overflow figure). Flow test and CFD simulation say that flow have stable state around suction and 20% of wave reduction effect at surface layer after surface water overflow.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.99-101
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• 2005

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the drivel board can be reduced.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.05a
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• pp.159-165
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• 2004

The shrinkages of injection molded parts are different in molding operational conditions and mold design. It also differs from resins. The shrinkages of injection molded parts for PBT (polybutylene terephthalate), PC (polycarbonate),and glass reinforced PBT and PC have been studied for various operational conditions of injection molding. The part shrinkage of crystalline polymer, PBT was higher than that of amorphous polymer, PC by about two times. The part shrinkages of both polymers decreased as glass fiber content increases. Higher Injection temperature and lower injection pressure resulted in a higher shrinkage in both PBT and PC resins. As mold temperature increases the part shrinkage of PC decreased. However, the part shrinkage of PBT increased as mold temperature increases. The part shrinkage of both PBT and PC resins decreased as gate size increases since the pressure delivery is mush easier for a larger gate size. The part shrinkage of flow direction was less than that of the perpendicular direction to the flow for both pure and glass fiber reinforced resins. The part shrinkage at the position close to the gate was less than that of the position far from the gate.

• Transactions of Materials Processing
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• v.13 no.6 s.70
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• pp.515-521
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• 2004

The shrinkages of injection molded parts are different in molding operational conditions and mold design. It also differs from resins. The shrinkages of injection molded parts fur PBT (polybutylene terephthalate), PC (polycarbonate), and glass reinforced PBT and PC have been studied for various operational conditions of injection molding. The part shrinkage of crystalline polymer, PBT was higher than that of amorphous polymer, PC by about two times. The part shrinkages of both polymers decreased as glass fiber content increases. Higher injection temperature and lower injection pressure resulted in a higher shrinkage in both PBT and PC resins. As mold temperature increases the part shrinkage of PC decreased. However, the part shrinkage of PBT increased as mold temperature increases. The part shrinkages of PBT and PC resins decreased as gate size increases since the pressure delivery is mush easier for a larger gate size. The part shrinkage of flow direction was less than that of the perpendicular direction to the flow for both pure and glass fiber reinforced resins. The part shrinkage at the position close to the gate was less than that of the position far from the gate.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Journal of Electrical Engineering and Technology
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• v.4 no.1
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.955-960
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• 2007

In this paper, the deviation of tunneling current for gate voltage has been investigated in double gate MOSFET developed to decrease the short channel effects. In device scaled to nano units, the tunneling current is very important current factor and rapidly increases,compared with thermionic emission current according to device size scaled down. We consider the change of tunneling current according to gate voltage in this study. The potential distribution is derived to observe the change of tunneling current according to gate voltage, and the deviation of off-current is derived from the relation of potential distribution and tunneling probability. The derived current is compared with the termionic emission current, and the relation of effective gate voltage to decrease tunneling current is obtained.