• Journal of Advanced Marine Engineering and Technology
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• v.37 no.1
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• pp.99-104
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• 2013

In this paper, we developed a fully integrated downconverter MMIC (monolithic microwave integrated circuit) including Lange coupler and output active balun for millimeter wave applications. Concretely, ${\lambda}$/4 transmission line was added to Lange coupler for size reduction of RF/LO input, and mixed RF/LO signals were applied to gate of the FET of mixer. Active balun was used at output port for a coupling of out-of-phase IF output signals. According to measured results, the proposed downconverter MMIC showed good RF performances. For example, the downconverter MMIC showed an LO leakage power of -25 dBc at IF output port, and a RF-LO isolation of 18 dB. Therefore, off-chip components such as LO rejection filters were not required for a normal operation of the proposed downconverter MMIC. The proposed downconverter MMIC showed a conversion gain of 10.3 dB at RF frequency of 63 GHz. The size of the downconverter MMIC including all active and passive components was $2.2{\times}1.4mm^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.163-163
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• 1999

MOSFET, MESFET 그리고 MODFET는 Logic ULSIs, high speed ICs, RF MMICs 등에서 중요한 역할을 하고 있으며, 그것의 gate electrode, contact, interconnect 등의 물질로는 refractory metal을 이용한 CoSi2, MoSi2, TaSi2, PtSi2, TiSi2 등의 효과를 얻어내고 있다. 그중 TiSi2는 비저항이 가장 낮고, 열적 안정도가 좋으며 SAG process가 가능하므로 simpler alignment process, higher transconductance, lower source resistance 등의 장점을 동시에 만족시키고 있다. 최근 소자차원이 scale down 됨에 따라 TiSi2의 silicidation 과정에서 C49 TiSi2 phase(high resistivity, thermally unstable phase, larger grain size, base centered orthorhombic structure)의 출현과 그것을 제거하기 위한 노력이 큰 issue로 떠오르고 있다. 여러 연구 결과에 따르면 PAI(Pre-amorphization zimplantation), HTS(High Temperature Sputtering) process, Mo(Molybedenum) implasntation 등이 C49를 bypass시키고 C54 TiSi2 phase(lowest resistivity, thermally stable phase, smaller grain size, face centered orthorhombic structure)로의 transformation temperature를 줄일 수 있는 가장 효과적인 방법으로 제안되고 있지만, 아직 그 문제가 완전히 해결되지 않은 상태이며 C54 nucleation에 대한 physical mechanism을 밝히진 못하고 있다. 본 연구에서는 증착 시 기판온도의 변화(400~75$0^{\circ}C$)에 따라 silicon 위에 DC/RF magnetron sputtering 방식으로 Ti/Si film을 각각 제작하였다. 제작된 시료는 N2 분위기에서 30~120초 동안 500~85$0^{\circ}C$의 온도변화에 따라 RTA법으로 각각 one step annealing 하였다. 또한 Al을 cosputtering함으로써 Al impurity의 존재에 따른 영향을 동시에 고려해 보았다. 제작된 시료의 분석을 위해 phase transformation을 XRD로, microstructure를 TEM으로, surface topography는 SEM으로, surface microroughness는 AFM으로 측정하였으며 sheet resistance는 4-point probe로 측정하였다. 분석된 결과를 보면, 고온에서 제작된 박막에서의 C54 phase transformation temperature가 감소하는 것이 관측되었으며, Al impuritydmlwhswork 낮은온도에서의 C54 TiSi2 형성을 돕는다는 것을 알 수 있었다. 본 연구에서는 결론적으로, 고온에서 증착된 박막으로부터 열적으로 안정된 phase의 낮은 resistivity를 갖는 C54 TiSi2 형성을 보다 낮은 온도에서 one-step RTA를 통해 얻을 수 있다는 결과와 Al impurity가 존재함으로써 얻어지는 thermal budget의 효과, 그리고 그로부터 기대할 수 있는 여러 장점들을 보고하고자 한다.

• Journal of IKEEE
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• v.19 no.1
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• pp.1-9
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• 2015

This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.

• Journal of Biosystems Engineering
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• v.35 no.2
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• pp.91-99
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• 2010

A Model of small scale total mixed rations(TMR) plant which can be utilized round bales was developed, tested and analyzed in this study. This study consist of two parts. One is development of a small scale TMR plant model which was already reported at the previous paper. This is the second part of the study. For the study, a series of tests of the model plant were performed and its costs was analyzed. Also, the break-even point of the model plant by comparing with market price of commercial TMR feed was determined. Results of the research are summarized as follows ; As the results of mixing test, the average coefficient of variation(CV) value for mixing of the feed was 13.0 % at the gate of the mixer. The production cost was estimated as 8,298 won/head for dairy cattle farm and 2,495 won/head for beef cattle farm, when producing 8 batch a day. Also, it is recommended to utilize the model plant when farm size is over 79 heads for dairy cattle farm and 113 heads for beef cattle farm. As an overall conclusion, the model plant designed for farm size TMR feed mill will be very useful model for both beef cattle and dairy farms in Korea. Also it is expected that the capital investment for the model plant can be recovered with 8 months compare with purchasing commercial TMR feed if the model plant feeds 1,000 beef cattle approximately.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.30-38
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• 2012

This paper presents packet detection, frequency offset estimation architecture and performance analysis for OFDM-based wireless personal area network (WPAN) systems. Packet detection structure is used to find the start point of a packet exactly in WPAN system as the correlation value passes the constant threshold value. The applied autocorrelation structure of the algorithm can be implemented simply compared to conventional packet detection algorithms. The proposed frequency offset estimation architecture is designed for phase rotation process structure, internal bit reduction to reduce hardware size and the frequency offset adjustment block to reduce look-up table size unlike the conventional structure. If the received signal can be compensated by estimated frequency offset through the correction block, it can reduce the impact on the frequency offset. Through the performance result, the proposed structure has lower hardware complexity and gate count compared to the conventional structure. Thus, the proposed structure for OFDM-based WPAN systems can be applied to the initial synchronization process and high-speed low-power WPAN chips.

• The Research Journal of the Costume Culture
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• v.23 no.1
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• pp.45-62
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• 2015

This study is to develop cultural products based on 'Jeju Choga', which means the traditional houses in Jeju. For the product development, old literature review, field surveys, and consumer surveys were employed. Through old literatures and field surveys, the unique and visual characteristics of Jeju Choga were confirmed: A thatched roof with lattice pattern, a side wall and fences with porous stones, a 'Jungnang' serving as a gate, and a 'Pungchai' preventing strong sola radiation and 'Ollai' meaning a narrow street in front of the Choga. As a results of consumer survey conducted before the development of products, consumers highly recognized and associated Jeju Choga as Jeju representative image. The six basic patterns of Jeju Choga were drawn and eight textile designs were created through the repeated arrangements of the basic patterns. Using the created textile designs and digital printing method, the eleven new fabrics with the patterns of Jeju Choga were developed. The various kinds of ten bags and tow wallets made with the new fabrics. As a result of consumer evaluation for the twelve products made in this study, the scores of preference and purchase intention were above the average work for the most products of them. In particular, the preference and purchase intention of the square shoulder bag, the big-size shopper bag, and the small-size cross bag were very positively evaluated. Therefore, it is confirmed that Jeju Choga could be very useful as a motif for the development of cultural products focusing on Jeju tourism souvenir market.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• International Journal of Computer Science & Network Security
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• v.23 no.7
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• pp.49-60
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• 2023

The amount of data generated by electronic systems through e-commerce, social networks, and data computation has risen. However, the security of data has always been a challenge. The problem is not with the quantity of data but how to secure the data by ensuring its confidentiality and privacy. Though there are several research on cloud data security, this study proposes a security scheme with the lowest execution time. The approach employs a non-linear time complexity to achieve data confidentiality and privacy. A symmetric algorithm dubbed the Non-Deterministic Cryptographic Scheme (NCS) is proposed to address the increased execution time of existing cryptographic schemes. NCS has linear time complexity with a low and unpredicted trend of execution times. It achieves confidentiality and privacy of data on the cloud by converting the plaintext into Ciphertext with a small number of iterations thereby decreasing the execution time but with high security. The algorithm is based on Good Prime Numbers, Linear Congruential Generator (LGC), Sliding Window Algorithm (SWA), and XOR gate. For the implementation in C, thirty different execution times were performed and their average was taken. A comparative analysis of the NCS was performed against AES, DES, and RSA algorithms based on key sizes of 128kb, 256kb, and 512kb using the dataset from Kaggle. The results showed the proposed NCS execution times were lower in comparison to AES, which had better execution time than DES with RSA having the longest. Contrary, to existing knowledge that execution time is relative to data size, the results obtained from the experiment indicated otherwise for the proposed NCS algorithm. With data sizes of 128kb, 256kb, and 512kb, the execution times in milliseconds were 38, 711, and 378 respectively. This validates the NCS as a Non-Deterministic Cryptographic Algorithm. The study findings hence are in support of the argument that data size does not determine the execution.