• Journal of Navigation and Port Research
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• v.26 no.5
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• pp.529-535
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• 2002

Design and implementation methodologies on the performance evaluation system of Two-Channel Ring-Core Flux-Gate Compass (TCRC FG-Compass) are described, with evaluation procedures and methods based on the polynomial regression models. Performance evaluation system consists of a step motor driving unit, a bearing transmitting unit and evaluation programs derived from polynomial regression formulae. Newly designed performance evaluation system enabled the accuracy of TCRC FG-Compass to be ascertained. It was confirmed that the size of residual deviation of TCRC FG-Compass is $2^{\circ}$, while that of the conventional one is $4^{\circ}$. In addition, the design methodology to the self estimation and correction of residual deviations is also discussed.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.558-563
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• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Journal of Power Electronics
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• v.16 no.3
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.228-231
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• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.5
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• pp.657-662
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• 2013

A size-reduced high frequency mixer designed by adopting artificial dielectric substrate is described in this work. The artificial dielectric substrate is composed by stacking the lower substrate in which a lot of metalized via-holes exist, and upper substrate on which microstrip lines are realized. The effective dielectric constant increases due to the inserted lots of via-holes, and this may be applied to size-reduction of high frequency circuits. In this work, in order to present an application example of size-reduction for active high frequency circuits using the artificial dielectric substrate, a 8GHz single gate mixer is miniaturized and measured. It is described that the basic circuit elements for mixers such as hybrid, low pass filter, and matching networks can be replaced by the artificial dielectric substrate for size-reduction. The final mixer has 55% of size compared to the normal one. The measured average conversion gain is around 3dB which is almost similar result as the normal circuit.

• Journal of Korean Society of Environmental Engineers
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• v.29 no.9
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• pp.1027-1034
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• 2007

This research was focused on the selective separation of $CO_2$ or $CH_4$ from mixture of these gases, by controlling the size of pore or pore gate. Pitch based activated carbon fibers(ACF) were used as adsorbents. The size of pore gate was controlled by the molecule having similar size to that of pore opening. After the adsorption of adsorbate on pore surface, planar molecules such as benzene and naphthalene covered the pore gate. The slow release of adsorbate from the pores covered by planar molecules makes apertures between planar molecules covering pore gate and this structure can be fixed by rapid pyrolysis. The control of pore gate using benzene as covering molecules could not accomplished due to the simultaneous volatilization of benzene and adsorbate$(CO_2)$ caused by similar temperatures of benzene volatilization and adsorbate desorption. Therefore we replaced benzene with naphthalene looking for the stability at a $CO_2$ desorption temperature. The naphthalene molecule was adsorbed on the ACF up to 15% of ACF weight and showed no desorption until $100^{\circ}C$, indicating that the molecule could be used as a good cover molecule. Naphthalene could cover almost all the pore gate, reducing BET surface area from 753 $m^2/g$ to 0.7 $m^2/g$. A mixed gas$(CO_2:CH_4=50:50)$ was adsorbed on the naphthalene treated OG-7A ACF. The amount of $CO_2$ adsorption increased with total pressure, whileas thai of $CH_4$ was not so much influenced on the pressure, indicating that $CO_2$ made more compounds on the ACF surface along with total pressure increase. The most $CO_2$ and the least $CH_4$ were adsorbed in the condition of 0.4 atm, resulting in the highly pure $CH_4$ left in ACF.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.4A
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• pp.337-342
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• 2010

Generally most sluice gates are closed and opened by a mechanical winch, a winch using an oil-pressure, or a winch mixing both. Because of their size and structure, they should be safely operated with more than two pulling devices helping each other. At the moment of their opening and closing, there usually occur some additional loads to the structure which cannot be exactly measurable at the stage of designing. Such additional loads can cause the sluice gate to be unbalanced and make it hard to open and close the gate, and by also overloading a winch, they can inflict a significant damage to the safety of the sluice gate. This paper explains a FDC(Force-Displacement Control) system which simultaneously considered the oil-pressure and displacement in order to evenly distribute the force and make a winch balanced at the opening and closing motion. This FDC system was implemented by means of the PID(Proportional Integral Derivative) function of XG 5000 program. It was experimented on a model of the sluice gate winch with the hydraulic oil pressure cylinder. The experiments showed that the developed FDC system made the winch of hydraulic oil pressure cylinder open and close cooperatively in spite of various external loads. Therefore the FDC system is proven effective when it is applied to a winch of sluice gate.