• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• 한국유체기계학회 논문집
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• 제14권5호
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• pp.39-47
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• 2011

Flow control range of valve, which is installed on pipeline, varies according to valve type, pipe diameter, pipe length, roughness, and elevation difference of both ends of pipeline. A lot of computation efforts and knowledge are needed to estimate flow control range of valve, considering above many parameters. The table of flow control range of each valve type is presented for convenience of pipeline design engineers who must make decision of valve size and type in this study. Also the reason that butterfly valve is recommended for flow control, and gate valve is forbidden is presented via quantification and figures in this study.

• 한국기계가공학회지
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• 제11권3호
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• pp.160-165
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• 2012

The packing, among the components comprising the gate valve, is used to sustain the air-tightness and the study on change of shape or pattern has been carried out to maximize the functions, but the study on changing the location or the size of the packing in a bid to prevent the freezing has rarely been implemented. Thus, This study is intended to evaluate the thermal strain of packing by heat transfer from territory of extremely low temperature as well as the temperature distribution to the upper part of the packing using numerical analysis method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.421-424
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• 2001

In this paper, We have designed and fabricated VCO in two way, the common source and common gate circuit for I local oscillator of 60 GHz wireless LAN system. The VCO employed a GaAs MESFET for negative resistance and a varactor diode for frequency tuning. The common gate VCO was measured the phase noise -112 dBc/Hz at the 1 MHz frequency offset. The output power and the second harmonic frequency suppression were 7.81 dBm and -29.3 dBc when tuning voltage was 3V, respectively. The total size of VCO was 28.6$\times$12.14 $\textrm{mm}^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Communications for Statistical Applications and Methods
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• 제18권2호
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• pp.257-266
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• 2011

The rapid development of airlines, has made airports busier and more complicated. The assignment of scheduled to available gates is a major issue for daily airline operations. We consider the over-constrained airport gate assignment problem(AGAP) where the number of flights exceeds the number of available gates, and where the objectives are to minimize the number of ungated flights and the total walking distance or connection times. The procedures used in this project are to create a mathematical model formulation to identify decision variables to identify, constraints and objective functions. In addition, we will consider in the AGAP the size of each gate in the terminal and also the towing process for the aircraft. We will use a greedy algorithm to solve the problem. The greedy algorithm minimizes ungated flights while providing initial feasible solutions that allow flexibility in seeking good solutions, especially in case when flight schedules are dense in time. Experiments conducts give good results.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.153-154
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• 2000

Large size poly-Si TFT-LCDs have been fabricated using p-channel thin film transistors for notebook PC application. We have designed and implemented the data sampling circuit and gate drivers that operate with low power consumption and high reliability. The gate driver has a redundant structure. We have realized the uniform and excellent display quality comparable to that of CMOS module. The reliability of panel is investigated and discussed by measuring the bias stability of transistors.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.68-72
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• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.613-616
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• 1999

An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.