• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.765-767
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off has been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Journal of architectural history
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• v.24 no.6
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• pp.45-55
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• 2015

After the Korean war, two major attempts were made to reconstruct Gwanghwamun Gate as an important part of Korea's lost cultural heritage. In December 2006, the Korean government replaced the concrete gate with a wooden one, yet traces of the attempts made in the 1960s to transform Gwanghwamun Gate and the main road remain to this day. At the time, the Third Republic of Korea, sought to legitimize itself in the name of modernity, and went on to modernize the architecture and urban landscape of Seoul. The location and design selected for the rebuilt Gwanghwamun illustrated the symbolic relationship between historic heritage and urban development. The reconstruction of the gate began as part of the Third Republic's project to restore the Central Administration Building and culminated in the transformation of the main road in front of the gate. By reconstructing the traditional gate using concrete, the military government intended to convey the message that we could inherit our proud tradition using modern materials, and that we should actively adopt the new technologies of the modern era. This study begins with the premise that the Gwanghwamun reconstruction project of 1968 represents the application of new technological thinking to Korea's architectural style, and has two objectives. The first is to summarize the reconstruction process and method using the records and drawings from the 1968 project, which was then under the leadership of architect Kang Bong-jin. The second is to analyze the characteristics of the architectural style and structure of the reconstructed Gwanghwamun so as to reinterpret the relationship between Korean tradition and modern technology.

• Journal of Korean Society of Steel Construction
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• v.25 no.6
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• pp.613-622
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• 2013

Numerous water gates have been constructed and are under construction for the control of water level because, due to the topographical characteristics of mountainous area, many small size rivers are developed in Korean peninsula. Among the water gates, movable water gates are more efficient to control water level than the fixed water gates. By the field application of the movable water gates, many problems associated with the fixed water gates have been mitigated. The problems include the bottom water pollution, the change of habitats for the riparian organisms, etc. This is the reason to increase the field application of movable water gates. In the paper we present the result of analytical investigation pertaining to the structural behavior of multistage overturning movable water gate which is one of the movable water gates. In the analytical investigations, the finite element analysis on the constructed water gate has been conducted for illustration purposes and it was found that the multistage movable water gate is much better than the fixed and/or existing movable water gates in the point of structural and environmental performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• Journal of the Korean Society of Radiology
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• v.13 no.5
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• pp.773-778
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• 2019

Images using X-rays are essential to diagnosis, but noise is inevitable in the image. To compensate for this, a total variation (TV) algorithm was presented to reduce the patient's exposure dose while increasing the quality of the images. The purpose of this study is to verify the effect on the image quality in radiographic imaging according to the thickness of the additional filtration plate through simulation, and to evaluate the usefulness of the TV algorithm. By using the Geant4 Application for Tomographic Emissions (GATE) simulation image, the actual size, shape and material of the Polymethylmethacrylate (PMMA) phantom were identical, the contrast to noise ratio (CNR) and coefficient of variation (COV) were compared. The results showed that the CNR value was the highest and the COV the lowest when applying the TV algorithm. In addition, we can acquire superior CNR and COV results with 0 mm Al in all algorithm cases.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.18-24
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• 2002

n this paper, we have fabricated pseudomorphic high electron mobility transistors (PHEMT) with a 0.2 ${\mu}{\textrm}{m}$ wide-head T-shaped gate using electron beam lithography by a dose split method. To make the T-shape gate with gate length of 0.2 ${\mu}{\textrm}{m}$ and gate head size of 1.3 ${\mu}{\textrm}{m}$ we have used triple layer resist structure of PMMA/P(MMA-MAA)/PMMA. The DC characteristics of PHEMT, which has 0.2 ${\mu}{\textrm}{m}$ of gate length, 80 ${\mu}{\textrm}{m}$ of unit gate width and 4 gate fingers, are drain current density of 323 ㎃/mm and maximum transconductance 232 mS/mm at $V_{gs}$ = -1.2V and $V_{ds}$ = 3V. The RF characteristics of the same device are 2.91㏈ of S21 gain and 11.42㏈ of MAG at 40GHz. The current gain cut-off frequency is 63GHz and maximum oscillation frequency is 150GHz, respectively.ively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.605-610
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• 2010

The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.

• Journal of Sensor Science and Technology
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• v.21 no.6
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.482-483
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• 2011

Graphene is a good candidate for the future nano-electronic materials because it has excellent conductivity, mobility, transparency, flexibility and others. Until now, most graphene researches are focused on the nano electronic device applications, however, biological application of graphene has been relatively less reported. We have fabricated a deoxyribonucleic acid (DNA) conjugated graphene field-effect transistor (FET) and measured the electrical transport characteristics. We have used graphene sheets grown on Ni substrates by chemical vapour deposition. The Raman spectra of graphene sheets indicate high quality and only a few number of layers. The synthesized graphene is transferred on top of the substrate with pre-patterned electrodes by the floating-and-scooping method [1]. Then we applied adhesive tapes on the surface of the graphene to define graphene flakes of a few micron sizes near the electrodes. The current-voltage characteristic of the graphene layer before stripping shows linear zero gate bias conductance and no gate operation. After stripping, the zero gate bias conductance of the device is reduced and clear gate operation is observed. The change of FET characteristics before and after stripping is due to the formation of a micron size graphene flake. After combined with 30 base pairs single-stranded poly(dT) DNA molecules, the conductance and gate operation of the graphene flake FETs become slightly smaller than that of the pristine ones. It is considered that DNA is to be stably binding to the graphene layer due to the ${\pi}-{\pi}$ stacking interaction between nucleic bases and the surface of graphene. And this binding can modulate the electrical transport properties of graphene FETs. We also calculate the field-effect mobility of pristine and DNA conjugated graphene FET devices.