• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.240-242
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• 2013

In this paper, novel Carbon Nanotube Gate-Elongated Tunneling Field Transistor(CNT G-E TFET) is proposed. This proposed device is designed to decrease off-current around 2~6 orders of magnitude compared to the gate-channel size matched TFET. Mechanism of CNT G-E TFET creates additional steps in energy band structure so that off-current can be reduced. Since CNT TFETs show a great probability for tunneling processes and they are beneficial for the overall device performance in terms of switching speed and power consumption, CNT G-E TFET looks pretty much promising.

• 대한전자공학회논문지SD
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• 제48권11호
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• pp.57-62
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• 2011

본 논문에서는 H.264, MPEG-2, MPEG-4, AVS, VC-1 코덱 표준의 가변 길이 복호화와 역 영자화가 가능한 MF-VLD(Multi-Format Variable Length Decoder)의 효율적인 구조에 대한 설계 방법을 제안 한다. 제안하는 MF-VLD는 MPSOC(Multiprocessor System on Chip)에 적합한 구조로 설계되었으며, 역 양자화된 데이터에 대해서 bit-plane알고리즘을 적용하여 AHB 버스의 폭을 줄였고, 내부 메모리의 사용량을 최소화 하기 위해 외부 SDRAM을 사용하였다. 또한, 코덱의 가변길이 복호화 모듈을 분리 가능한 구조로 설계하여 상황에 따라 가변길이 복호화 모듈에 대한 추가 및 제거가 용이 하도록 하였다. 설계된 MF-VLD는 0.18 ${\mu}m$ 공정에서 200 MHz의 속도로 동작하며, 사이즈는 약 657 K 게이트 이고, 사용되는 메모리는 약 27K 바이트 이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.49-52
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• 2001

The electrochemical characteristics of Alalloy thin film with low impurity concentrations AIZr deposited by using do magnetron co-sputtering deposition are investigated for the applications as gate bus line in the TFT-LCD panel. AlZr thin films were deposited various atomic percent of Zr. For increasing Zr atomic percent the hillock density was decreased and the resistivity was increased. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at 300 $^{\circ}C$for 20 min.. Moreover, the resistivity of AIZr does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AIZr(at.0.9%) is found to be hillock free. The electrode potentials of AIZr were less than ITO's (-1.4V) and the etching rate of AIZr(at.0.9%) was 3.8587ng/sec. in KOH(10%) solution. Caculation results reveal that the AIZr(at.0.9%) thin film can be applicable to gate line of 25" UXGA class TFT-LCD panels and can not be applicable to data line.line.

• 대한전자공학회논문지SD
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• 제38권12호
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• pp.14-24
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• 2001

본 논문에서는 1.9 GHz대의 down converting 믹서를 능동 cascode 구조의 MMIC로 상용 설계 툴을 이용하고 일반적인 증폭기의 설계 방법을 응용한 시뮬레이션을 통하여 설계, 제작, 측정 및 분석하였다. 본 연구에서는 특히 능동 믹서의 설계과정 및 측정 결과를 자세히 기술하였다. 본 연구에서 사용된 능동소자는 Gate Length 0.5 ${\mu}$m, Gate Width 300 ${\mu}$m 인 GaAs MESFET이다. 개발된 회로는 3V 의 전원의 7.5 mA 의 전류를 소모하는 저전력소모의 MMIC 능동믹서로 변환 이득이 6.63 dB 이고 최저 잡음지수는 5.06 dB이며 Output $3^{rd}$ Order Intercept Point는 6.4 dBm 이다. 제작된 칩의 크기는 가로 1.86 mm 세로 1.28 mm 이다.

• 한국정보통신학회논문지
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• 제14권10호
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• pp.2305-2309
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• 2010

본 연구에서는 상단게이트와 하단게이트를 갖는 더블게이트 MOSFET에서 채널길이와 채널두께의 비에 따른 문턱전압의 변화에 대하여 분석하였다. 더블게이트 MOSFET는 두개의 게이트를 가지고 있기 때문에 전류제어 능력이 기존 MOSFET의 두배에 가깝고 나노소자에서 단채널효과를 감소시킬 수 있다는 장점이 있다. MOSFET에서 채널길이와 채널두께는 소자의 크기를 결정하며 단채널효과에 커다란 영향을 미치고 있다. 채널길이가 짧아지면 서 채널두께와의 비에 따라 단채널효과 중 문턱전압의 변화가 크게 영향을 받고 있다. 그러므로 이 연구에서는 DGMOSFET에서 채널길이와 채널두께의 비를 변화시키면서 문턱전압의 변화와 드레인 유기장벽감소현상을 분석할 것이다.

• 한국농공학회지
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• 제45권6호
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• pp.109-118
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• 2003

As a fundamental research to establish a safety operation plan for irrigation dams, this study presents hydrologic analysis conducted in Sungju Dam watershed based on various rainfall data. Especially those reservoirs without flood control feature are widely exposed to the risk of flooding, a safe and optimized operation program need to be improved against arbitrary flooding. In this study, reservoir routing program was developed and simulated for reservoir runoff estimation using WMS hydrology model. The model simulated the variations of reservoir elevation under the condition of open or closed emergency gate. In case of closed emergency gate, water surface elevation was given as 193.15 m, and this value exceeds the dam crest height by 1.65 m. When the emergency gate is open, the increment of water surface elevation is given as 192.01 m, and this value exceeds dam crest height by 0.57 m. As an alternative plan, dam height increase can be considered for flood control under the PMP (Probable Maximum Precipitation) condition. Since the dam size is relatively small compare to the watershed area, sound protection can be expected from the latter option rather than emergency gate installation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.675-678
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• 2003

We studied the electrical characteristics of pentacene-based organic field-effect transistors (FETs) with polymethyl methacrylate (PMMA) or poly-4-vinylphenol (PVP) as the gate insulator. PMMA or PVP was spin-coated on the indium tin oxide glass substrate that serves as gate electrodes. The source-drain current dependence on the gate voltage shows the FET characteristics of the hole accumulation type. The transistor with PVP shows a higher field-effect mobility of 0.14 $cm^{2}/Vs$ compared with 0.045 $cm^{2}/Vs$ for the transistor with PMMA. The atomic force microscope (AFM) images indicate that the grain size of the pentacene on PVP is larger than that on PMMA. X-ray diffraction (XRD) patterns for the pentacene deposited on PVP exhibit a new Bragg reflection at $19.5{\pm}0.2^{\circ}$, which is absent for the pentacene on PMMA. This peak corresponds to the flat-lying pentacene molecules with less intermolecular spacing.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1364-1366
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• 1998

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay. pixel charging ratio, level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2009년도 춘계학술대회 논문집
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• pp.435-436
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• 2009

In the effort on cost reduction in marine equipment company, the medium sized impeller blade ($500mm{\times}200mm{\times}20mm$) of an axial flow pan was manufactured by the high pressure die casting, with which was replaced the gravity die casting. High pressure die casting is a practical alternative because of some advantages such as excellent accuracy and smooth cast surface as well as cost reduction if a certain amount of porosity in the parts can be minimized. In order to reduce the porosity in the center of the neck which is thickest region of the impeller blade, the several gate designs were proposed in this work. The flow simulations for each gate design were performed and then the optimal design was determined by considering the air pressure distribution in neck section. Finally, the size of porosity in the neck of the die cast impeller blade for optimal design was less than 1mm, which satisfied the requirement.

• 한국군사과학기술학회지
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• 제17권1호
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• pp.108-114
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• 2014

This paper describes a method to set an intensity-based initial validation gate for tracking filter while preserves the ability of tracking a target with maximum speed. First, we collected real data set of signal versus distance of an airplane target. And at each data point, we computed maximum distance the target can move. And a function is modeled to expect the maximum moving pixels on the lateral direction based on the intensity of the detected target in IR image sequence. The initial prediction error covariance can be computed using this function to decide the size of the initial validation gate. The simulation results show the proposed method can set the appropriate initial validation gates to track the targets with the maximum speed.