• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.5
• /
• pp.509-521
• /
• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.627-630
• /
• 1991

This study is about vector controlled inverter for high quality elevator drive that is to improve the settling accuracy of elevator car and passenger's comfort in commercial buildings. In this study, an instantaneous space vector control type inverter was used to reduce the torque ripple ant to improve the velocity follow-up. This method calculates Instantaneous actual output torque and flux of induction motor by voltage and current, then compares them with a reference values by a speed regulator. The outputs of comparators select a switching mode, for an optimal voltage vector. Also, this study used IGBT (Insulated Gate Bipolar-Transistor), a high speed switching element, to reduce sound noise level, and DSP (Digital Signal Processor) was used to improve the reliability of the control circuit by fully digitalization.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.1176-1178
• /
• 1992

This paper shows enhanced working performance of the battery fork-lift truck by developing the IGBT full bridge dc-dc convertor using one-chip micro-processor. The PWM pulse is generated from a 16 bit one-chip micro-processor for the speed control of DC motor. In order to ensure the operation of IGBT and motor pecewisely, IGBT gate drive circuit was designed by using current limiting IC and hige voltage limit IC. And also It is able to regenerative braking.

• Journal of the Korean Society of Industry Convergence
• /
• v.2 no.2
• /
• pp.103-108
• /
• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.9
• /
• pp.107-116
• /
• 1996

In the stochastic structure for doing exact calculationk, an input number must be changed to a pulse stream. Because the performance of random number generator (RNG) is controlled by its initial condition, we suggested newly modified cellular automata (MCA) which is uses a counter for boundary condition. We compared newly suggested MCA RNG to previously reported RNGs using the AND gate passing outputs which have the same meaning of multiplication in the stochastic calculation. In order to use stochastic we studied about the method, one large RNG can generate many small random numbers. In this method, RNG must have large drive capabilities for many input comparator. So we studied about drive capabilities using BiCMOS circuit and CMOS circit by SPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.10-15
• /
• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Proceedings of the KSR Conference
• /
• 2005.11a
• /
• pp.671-675
• /
• 2005

In this paper, Development of propulsion system using IPM(Intelligent Power Module) for DC electric vehicle is proposed. Designed propulsion system is comprised of inverter stack which includes 6 IPM, BCH(Breaking Chopper) unit, FC(Filter Capacitor), Control unit. IPM can compose propulsion system simple by including gate drive circuit and protection circuit. Inverter stack is designed as a simple structure using IPM and non clamp capacitor. VVVF Inverter control is used the vector control strategy at low velocity region and slip frequency-control strategy at high velocity region. Designed propulsion system proves the performance through test and revenue service.

• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.510-511
• /
• 2014

본 논문에서는 3-레벨 T-type 인버터에 적용 가능한 저가형 게이트 드라이버 회로를 설계하였다. 게이트 드라이버 회로는 구조가 간단하고 가격 대비 효율적인 부트스트랩 회로가 적용되었다. 3-레벨 NPC 인버터와 비교했을때 T-type 인버터는 구조적 특징으로 인해 NPC 인버터와는 다른 게이트 드라이브 회로가 필요하다. 그러므로 본 논문에서는 T-type 인버터에 적용되는 부트스트랩 게이트 드라이버 회로를 설계하였으며 안정적인 회로 동작을 위한 부트스트랩 캐패시터의 용량 선정식을 제안하였다. 설계한 게이트 드라이버 회로는 시뮬레이션을 통해 검증하였다.

• ETRI Journal
• /
• v.42 no.5
• /
• pp.773-780
• /
• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Journal of Advanced Marine Engineering and Technology
• /
• v.30 no.8
• /
• pp.901-906
• /
• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.