• 전자공학회논문지A
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• 제33A권2호
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.535-539
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• 2001

The aim of this paper presents to develop a computer-aided design system for water gate on AutoCAD R2000system. The developed system has been written in AutoCAD and Visua ILISP with a personal computer, and is composed four modules which are the gate-lifter input module, guide-frame input module, template input module and upgrade module. Based on knowledge-based rules, the system is designed by considering several factors, such as width and height of a water gate, material, object of product and maximum depth of water. Employing the developed system enable the designer and manufactures of water gate to be more efficient in this field, and its potential capability for enhancement included FEM(Finite Element Method) and quotation system.

• 한국광학회:학술대회논문집
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.302-310
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• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.889-892
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• 2009

We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

• 한국정보통신학회논문지
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• 제18권6호
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• pp.1422-1428
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 하단 게이트전압에 대한 문턱전압이동 현상에 대하여 분석하였다. 비대칭 DGMOSFET는 4단자소자로서 상단과 하단의 게이트단자에 별도의 전압을 인가할 수 있으므로 하단게이트전압의 변화가 문턱전압에 영향을 미칠 것이다. 그러므로 단채널효과로 알려져 있는 문턱전압 이동현상이 하단게이트전압에 의하여 감소할 수 있는지를 관찰하고자 한다. 이를 위하여 문턱전압이하영역에서의 차단전류모델을 제시하였으며 차단전류가 채널폭 당 $10^{-7}A/{\mu}m$일 경우의 상단게이트 전압을 문턱전압으로 정의하여 채널길이 및 채널두께의 변화에 따라 하단게이트 전압의 변화에 대한 문턱전압의 이동현상을 관찰하였다. 결과적으로 하단게이트전압은 문턱전압이동현상에 커다란 영향을 미치는 것을 알 수 있었으며, 특히 단채널효과가 심각하게 발생하고 있는 채널길이 및 채널두께 영역에서는 더욱 큰 영향을 미치고 있다는 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• 건축역사연구
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• 제8권1호
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• pp.41-52
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• 1999

This study aims to infer the plan and location of the government office building in Chongju Castle in the Late Yi-dynasty. The conclusion is as follows: 1. The Chongju Castle Map(淸州邑城圖, late in the 18th century, hereinafter referred to CCM) provides the detail arrangement and location of Government Office Building in Chongju Castle. And the road structure and plan of the CCM is almost same with the present time. 2. As compared with CCM and a Chongju-land Registration Map(淸州面地籍原圖, 1913, CRM) to infer the location of the traditional government office building in Chongju Castle, the building locations of Gaek-Sa(客舍) Donghun(東軒)'s region in CCM are almost accordance with today's. But those of Byungyoung(兵營) Group's region are represented by a little error. So the locations of Byungyoung(兵營) Group's region rearranged, moved down to be in accordance with the approach circulation of Main Gate(閉門樓) which is shown in CRM. 3. The records, on the plan of the traditional government office building in Chongju Castle, have proved that the plan of Gaek-Sa was a width of 11 bay and a depth of 2 bay. A width of 3 bay drawn in CCM, the present plan of Donghun is a width of 7 bay and a depth of 4 bay. The main building and especially the double-storied Main Gate($4{\times}3$) of Byungyoung Group are exactly in keeping with the present road structure.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• 대한전자공학회논문지
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• 제23권6호
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• pp.807-813
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• 1986

Measurements of interface states in a MOS capacitor by DLTS system using wideband monophase lock-in amplifier are discussed. A new signal analysis method that takes into account the bias pulse width and the gate off width is presented to remove the errors in the measured parameters of interface states resulting from the traditional method which neglects the effect of those widths. Theoretical calculations are made for the parameters related to the rate window, signal to noise ratio, and the energy resolution. On the grounds of this discussion, interface states of the MOS capacitor on p-type substrate of (110) orentation are measured with the optimal gate-off width with respect to the S/N ratio and the energy resolution. The results are interface state density of the order of 10**10 (cm-\ulcornereV**-1) to 10**11 (cm-\ulcornereV**-1) in the energy range of Ev+0.15(dV) to Ev+0.5(eV), and constant capture cross section of the order of 10**-16 (cm\ulcorner.