• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.389-390
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• 2008

The dependence of $f_T$ and $f_{max}$ on the unit finger width is measured and analyzed for $0.13{\mu}m$ MOSFETs. The increase of $f_T$ at narrow width is attributed by the parasitic gate-bulk capacitance, and the decrease of $f_T$ at wide width is generated by the reduction of increasing rate of $g_{mo}$. The increase of $f_{max}$ at narrow width is originated from the abrupt reduction of gate resistance due to the non-quasi-static effect. These analysis results will be valuable information for layout optimization to improve $f_T$ and $f_{max}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.14-24
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• 2001

An active MMIC L-band down converting mixer was designed by using GaAs FET with 0.5 ${\mu}$m gate length and 300 ${\mu}$m gate width. Main circuit topology was cascoded two active FETs. It consumed only 7.5 mA with 3V DC voltage supply. Conversion gain of 6.63 dB, minumium noise figure of 5.06 dB and Input $3^{rd}$ Order Intercept Point of 6.4 dBm were obtained. The chip size is 1.86 mm ${\times}$ 1.28 mm.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2061-2062
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• 2006

a-Si(amorphous silicon) TFT(thin film transistor)는 TFT-LCD(liquid crystal display)의 화소 스위칭(switching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 ASG(amorphous silicon gate) 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압(Vth)의 이동이다. 특히 고온에서는 문턱 전압의(Vth) 이동이 가속화 되고, Ioff current가 증가 하게 되고, 저온($0^{\circ}C$)에서는 전류 구동능력이 상온($25^{\circ}C$) 상태에서 같은 게이트 전압(Vg)에 대해서 50% 수준으로 감소하게 된다. 특히 ASG 회로는 여러 개의 TFT로 구성되는데, 각각의 TFT가 고온에서 Vth shift 값이 다르게 되어 설계시 예상하지 못 한 고온에서의 화면 무너짐 현상 즉 고온 노이즈 불량이 발생 할 수 있다. 고온 노이즈 불량은 고온에서의 각 TFT의 문턱전압 및 $I_D-V_G$ 특성을 측정한 결과 고온 노이즈 불량에 영향을 주는 인자가 TFT의 width와 기생 capacitor비 hold TFT width가 영향을 주는 것으로 실험 및 시뮬레이션 결과 확인이 되었다. 발생 mechanism은 ASG 회로는 AC 구동을 하기 때문에 Voff 전위에 ripple이 발생 되는데 특히 고온에서 ripple이 크게 증가 하여 출력 signal에 영향을 주어 불량이 발생하는 것을 규명하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.5
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• pp.621-627
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• 2011

In this paper, we analysed performance for on-wafer GaN HEMT using load-pull in X-band, and studied optimum impedance point based on analysis result. We suggested method of optimum performance device by analysis of optimum impedance for solid state device on-wafer condition before packaging. The measured device is gate length 0.25um, and gate width is 400um, 800um. device 400um is performed $P_{sat}$=33.16dBm, PAE=67.36%, Gain=15.16dBm, and device 800um is performed $P_{sat}$=35.91dBm, PAE=69.23%, Gain=14.87dBm.

• Journal of The Korean Society of Agricultural Engineers
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• v.54 no.3
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• pp.133-139
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• 2012

Dynamic characteristic of lift gate supported by plane truss is studied by a model test scaled with the ratio of 1 : 31.25 in the four major rivers project. The vibrations of gate supported by the plane truss is assessed in comparison with those of gate supported by the space truss which was tested formerly. The gate model is made of acryl panel and calibrated by lead. A model test is conducted under the different gate opening and upstream water levels conditions in the concrete test flume dimensioned 1.6 m in width, 0.8 m in height and 24 m in length. In order to verify the model, natural frequencies of the model gate are measured, and compared with the numerical results. The vibrations of gate model supported by the plane truss in opening height of 1.0 cm~2.0 cm shows greater than one supported by the space truss. It is found that the gate model supported by the plane truss is less desirable than one supported by the space truss. thus, the latter type of gate model is requested to design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1579-1587
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• 1999

Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.889-893
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• 2015

In this work, the characteristics of GIDL current in nanowire GAA MOSFET with different channel width and hot carrier stress. When the gate length is fixed as a 250nm the GIDL current with different channel width of 10nm, 50nm, 80nm, and 130nm have been measured and analyzed. From the measurement, the GIDL is increased as the channel width decreaes. However, the derive current is increased as the channel width increases. From measurement results after hot carrier stress, the variation of GIDL current is increased with decreasing channel width. Finally, the reasons for the increase of GIDL current with decreasing channel width and r device. according to hot carrier stress GIDL's variation shows big change when width and the increase of GIDL current after hot carrier stress are confirmed through the device simulation.