• 한국해양환경ㆍ에너지학회지
• /
• 제2권2호
• /
• pp.49-59
• /
• 1999

낙동강 하구역은 담수와 해수가 만나 복잡한 순환양상을 보이는 지역이다 낙동강 하구역은 하구둑의 건설로 혼합체계와 순환양상이 많이 변하였다. 논 연구에서는 낙동강 하구둑 하류부의 해양 물리 환경 변화론 하구둑의 수문개폐에 초점을 맞춰 분석하였다. 관측과 분석에는 3가지의 경우로 나누었다. 1. 평상시 (조시에 따라 수문 개폐) 2. 홍수시 (수문 완전 개방) 3. 갈수시(수문이 완전히 닫혔을시).

• 센서학회지
• /
• 제27권6호
• /
• pp.362-367
• /
• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 한국기계가공학회지
• /
• 제20권2호
• /
• pp.86-92
• /
• 2021

Usually, the die-cast components used in small mobile devices require finishing processes, such as computer numerically controlled coating. In such cases, porosity is the most important defect. The shape of the molten aluminum that passes through the runner and gate in a mold is the one of the factors that influences gas porosity. To define the spurt index, which numerically indicates the shape of molten aluminum after the gate, Reynolds number and Ohnesorge number are used. Before die fabrication, computer-aided engineering analysis is performed to optimize the filling pattern. Finally, X-ray and surface inspection are performed after casting and machining to evaluate how the spurt index affects porosity and other product parameters. Based on the results obtained herein, a new gating system design process is suggested.

• 한국산업정보학회논문지
• /
• 제16권5호
• /
• pp.1-8
• /
• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.470-473
• /
• 2002

A communication-aid circuit to detect eye-gazed patterns is proposed in this paper. The circuit is an analog-digital mixed system. By determining the direction of eye-gazed pattern, the circuit detects an eye-gazed pattern from 2-dimensional arrayed patterns on a syllabary. Different from conventional systems, the syllabary is moved to overlap the eye-gazed pattern with the center coordinate of screen. Thus, the proposed circuit can avoid a complex calculation of the distance between the eye-gazed point and the center coordinate. Furthermore: an economical size of hardware can be provided since no full-adders are required by employing floating-gate MOSFBT's. The validity of the cricuit design is confirmed by computer simulations. Furthermore, to implement onto an IC chip, the layout design is performed by using a CAD tool, MAGIC.

• 사물인터넷융복합논문지
• /
• 제6권1호
• /
• pp.97-102
• /
• 2020

사물인터넷 환경에서 다중 객체의 스위치 제어는 고전압을 구동하기 위해 레벨 시프터가 있는 여러 솔리드 스테이트 구조로써 낮은 ON 저항과 양방향 릴레이 MOS 스위치를 통합했으며 외부 직렬 논리 제어에 의해 독립적으로 제어되어야 한다. 이 장치는 의료용 초음파 이미지 시스템, 잉크젯 프린터 제어 등의 IoT 기기뿐만 아니라, 켈빈 4 단자 측정을 사용한 PCB 개방 / 단락 및 누출 테스트 시스템과 같은 저전압 제어 신호에 의한 고전압 스위칭 제어가 필요한 응용 제품에 사용하도록 설계되었다. 이 논문에서는 FPGA (Field Programmable Gate Array) 테스트 패턴 생성을 사용한 아날로그 스위치 제어 블록의 구현 및 검증에 대하여 고찰하였다. 각 블록은 Verilog 하드웨어 설명 언어를 사용하여 구현된 후 Modelsim에 의해 시뮬레이션 되고 FPGA 보드에서 프로토타입화 되어 적용되었다. 제안된 아키텍처는 IoT 환경에서 여러개의 개체들을 동시에 제어하여야 하는 분야에 적용할 수 있으며 유사 형태의 IC를 테스트하기 위해 제안된 패턴 생성 방법을 적용할 수 있다.

• 대한전자공학회논문지SD
• /
• 제48권10호
• /
• pp.67-71
• /
• 2011

디지털 도어락, 디지털 카메라, 비디오 감시 시스템 등에서 사용되는 기존의 얼굴 검출 시스템은 비교적 낮은 해상도의 영상 처리를 사용하고 있으며 이를 위해서 소프트웨어 기반의 구현을 하고 있다. 하지만 이 경우에는 높은 해상도를 위한 얼굴 검출이 어려울 뿐만 아니라 수행해야할 영산 처리 양이 많기 때문에 실시간으로 얼굴을 검출하는데 어려움이 있다. 실시간 임베디드 시스템에서 HD(High Definition) 영상을 위한 효과적인 얼굴 검출을 위해서는 하드웨어적인 접근이 필요하다. 이에 본 논문에서는 얼굴 검출을 위해 사용되는 전처리 과정 중에 하나이며 처리시간이 많이 소요되는 국부 이진 패턴(LBP, Local Binary Pattern) 연산을 하드웨어 구조를 제시하고 설계했다. 그리고 제시한 하드웨어 구조를 FPGA(Field Programmable Gate Array) 칩을 통해서 구현 및 검증을 통해 고해상도 HD급 영상에서 효율적인 얼굴 검출이 가능 한 것을 확인했다.

• 전자공학회논문지A
• /
• 제28A권12호
• /
• pp.65-72
• /
• 1991

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.

• 전자공학회논문지A
• /
• 제31A권12호
• /
• pp.38-43
• /
• 1994

GaAs and AlGaAs layers were grown by Molecular Beam Epitaxy (MBE) to fabricate hith performance GaAs MESFETs. Optimum growth temperatures were found to be 600$^{\circ}C$ from their Hall measurement data. MESFETs with the gate legth of 1${\mu}$m and the gate width of 100.mu.m were fabricated on the MBE-grown GaAs layters which has i-GaAs buffer layer and characterized. Knee volgate and mazimum transconductance of the devices were 1V, 224mS/mm, respectively. Cut-off frequency at on-wafer measuring pattern was measured to be 18 GHz. The MESFET with the 1${\mu}$m -thick i-Al$_{0.3}Ga_{0.7}$As buffer layer between nactive and i-GaAs was fabricated on order to reduce the leakage current which flows through the i-GaAs buffer layer. Its output resistance was 2.26 k${\Omega}$.mm which increased by a factor of 15 compared with the MESFET without i-Al$_{0.3}Ga_{0.7}$As buffer layer.

• 한국기계가공학회지
• /
• 제11권3호
• /
• pp.160-165
• /
• 2012

The packing, among the components comprising the gate valve, is used to sustain the air-tightness and the study on change of shape or pattern has been carried out to maximize the functions, but the study on changing the location or the size of the packing in a bid to prevent the freezing has rarely been implemented. Thus, This study is intended to evaluate the thermal strain of packing by heat transfer from territory of extremely low temperature as well as the temperature distribution to the upper part of the packing using numerical analysis method.