• Journal of the Semiconductor & Display Technology
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• v.19 no.1
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• pp.61-66
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• 2020

Threshold voltage shift occurring during operation is implemented in a SPICE simulation tool. Among the shift models the stretched-exponential function model, which is frequently observed from both single-crystal silicon and thin-film transistors regardless of the nature of causes, is selected, adapted to transient simulation, and added to BSIM4 developed by BSIM Research Group at the University of California, Berkeley. The adaptation method used in this research is to select degradation and recovery models based on the comparison between the gate and threshold voltages. The threshold voltage shift is extracted from SPICE transient simulation and shows the stretched-exponential time dependence for both degradation and recovery situations. The implementation method developed in this research is not limited to the stretched-exponential function model and BSIM model. The proposed method enables to perform transient simulation with threshold voltage shift in situ and will help to verify the reliability of a circuit.

• ETRI Journal
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• v.33 no.3
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• pp.393-400
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• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.339-340
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• The KSFM Journal of Fluid Machinery
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• v.9 no.5 s.38
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• pp.14-21
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• 2006

In general, the hollow jet valve, the fixed cone valve had been used for the urgency released or maintenance of the flow rate. Nowadays, the butterfly valve, the gate valve are applied in economic performance and operation maintenance more than the hollow jet valve, the fixed cone valve. However, in the case of butterfly valve, it should be required the strict application standard to the cavitation coefficient because the structural axis and disk were situated in pipe channel and the occurring the shock problem by Karman Vortex. Therefore, there were investigated the valve cavitation and accident investigation by field survey to establish the applicable extensibility of the urgency released valve as the preliminary study.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.112-113
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• 2013

본 논문에서는 부트스트랩 게이트 드라이브 회로가 적용된 3-레벨 NPC 인버터의 전동기 저속 운전에 적용하기 위한 PWM 스위칭 전략을 제안한다. 3-레벨 NPC 인버터를 이용하여 전동기를 제어할 경우, 일반적으로 구현의 편리성 때문에 CBPWM이 주로 사용된다. CBPWM 중 Unipolar 방법이 주로 사용되지만 부트스트랩 회로를 적용한 3-레벨 NPC 인버터의 전동기 저속 운전 시 부트스트랩 캐패시터 방전에 의한 전압 감소 크기가 증가한다. 캐패시터 전압이 정상적인 인버터 동작을 위한 한계 전압 이하로 감소하면 정상적인 제어는 불가능하다. 따라서 본 논문에서는 부트스트랩 회로가 적용된 3-레벨 NPC 인버터의 전동기 저속 운전에 적용하기 위한 PWM 스위칭 전략에 대해 제안 하였으며 시뮬레이션을 통하여 그 타당성을 증명하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.55-58
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• 1998

Recently, neural networks with self-adaptability like human brain have attracted much attention. It is desirable for the neuron-function to be implemented by exclusive hardware system on account of huge quantity in calculation. We have proposed a novel neuro-device composed of a MFSFET(ferroelectric gate FET) and oscillation circuit with CUJT(complimentary unijuction transistor) and PUT(programmable unijuction transistor). However, it is difficult to preserve ferroelectricity on Si due to existence of interfacial traps and/or interdiffusion of the constitutent elements, although there are a few reports on good MFS devices. In this paper, we have simulated CUJT and PUT devices instead of fabricating them and composed oscillation circuit. Finally, we have resented, as an approach to the MFSFET neuron circuit, adaptive learning function and characterized the elementary operation properties of the pulse oscillation circuit.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.